# Design of 16 Bitadder for Residue Number System Using A Novel Modulo 2n-2k-1

DOI : 10.17577/IJERTV3IS030857

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#### Design of 16 Bitadder for Residue Number System Using A Novel Modulo 2n-2k-1

Akash. G

1 PG Scholar, Final Year, Department Of Electronics and Communication Engineering, Sri Krishna College of Engineering & Technology, Coimbatore.

Abstract – To design a 16 bit adder using this novel modulo 2n-2k- 1 is nothing but introducing a carry correction term K to reduce area in terms of any bit adder. Here Conventional Carry Select Adder is used to design a novel modulo 2n-1 and modified conventional carry select adder to design a novel modulo 2n-2k-1 adder and so on. XILINX using Spartan 2 devices is used to illustrate the area report which gives complete information regarding the no of slices available and used respectively. Power is analyzed in report views to make this modulo adder more efficient respectively.

Keywords- area, power, CSA, MCSA

1. INTRODUCTION

normally in calculators modulo addition is performed by taking the sum of two numbers and dividing by 2 that willgenerate the result with quotient and remainder. The particular remainder is taken as the MOD value. If there is no remainder then there is no possibility of MOD application. In the design of novel modulo design residue number system is used to implement the design in binary representation .This novel modulo is implemented in MODELSIM which perform operation by taking each bit separately. The corresponding results are generated only after each clock cycle rate. The corresponding formulas which are applied to implement are shown in (1)

C= (A+ B) m = A+B A+B+T<2n

(A+B+T)m A+B+T>2n (1)

The value of T is generally T=2n-m. Here the value of n is 16 and the value of 216 is 65,535. If both the bit integers of A and B is less than 65,535 then the first case is followed .If both the bit integers are greater than 65,535 then the second case shown in (1) is followed. T is the carry correction term used to implement the 16 bit adder respectively.

Adder architectures comprises of different set of adders which usually vary in architecture design and performance parameter. Normally area and speed efficiency should be simultaneously satisfied for the novel modulo. First adder architectures are discussed to find the adder which is suitable for 2n-2k-1 design modulo.

C0 D0 C1 D1 C2 D2 C3 D3 CIN

Cout

S0 S1 S2 S3

Fig.1.Block Diagram of Ripple Carry Adder

The rippling pattern is almost similar to RCA but it usually generates worst case delay for the corresponding 4-bit adders. The main principle is only the carry is skipped over the entire group but not the operations which are involved in it. Sometimes while skipping the carry over the entire group, area will be doubled because some of the adders require two cycles for one bit operation.

Carry Look-Ahead is illustrated mainly in prefix tree structures due to cross- layer networks. Ripple carry addition cannot be performed for cross networks because cross networks usually originate from two different layers .In order to perform operation between two different layers only generation and propagation of bits is employed. The first layer bit can be taken as (g0,p0) and the second layer bit can be taken as (g1,p1).Then the corresponding operation has to be employed. Architecture of carry look ahead varies slightly

from ripple carry adder in the generation of bit which is independent of the previous bit position. When this design is implemented in 2n-2k-1 modulo design first the word size followed by complexity increase would result in area increase obviously.

Generally in the first 4 bit addition with carry correction term will generate the carry value of 0 and without the carry correction term will generate the value 1.CSA function is to accept both the values of 0 and 1 and pass it to MUX to select the possible output.

Suppose in the detection of the first 0 bit the invert operation has to be employed only if all the bits generated are 0. Otherwise all the bits has to be kept as non-invert and perform the operation IF there is no zero bit there is no possibility of detection then the normal sum is performed.

3.3 CONVENTIONAL CARRY SELECT ADDER FOR 2n-1

(A+B) MOD (2n-1) = (A+B) A+B<2n

(A+B+1)MOD2n A+B>2n (2)

FIR ST 4 BIT

SEC OND 4 BIT

THI RD 4 BIT

FOU RTH 4 BIT

A4 B4 A3 B3 A2 B2 A1 B1 0 0 0

RCA

I/

RCA RCA P

THI RD 4 BIT

FOU RTH 4 BIT

1 1 1

SEC

3.2 Binary To Excess-1 Converter

Digital electronics often employ the term binary to excess-3 converter. Generally in 4bit adder it has to be shifted to 3 bits. Some of the logic gates which are employed are and, not, ex- or. Binary to exces-1 will shift to 1 bit in order to convert the given 4 bit into 5 bit. Even though the use of MUX seems to be costly in terms of hardware description. Novel modulo needs to be implemented in terms of area and speed MUX is necessary for the implementation.

RCA RCA

OND 4 BIT

RCA

The operation is illustrated below in the fig 2

B0 B1 B2 B3 B4 B0 B1 B2 B3

4 bit RCA

5-bit BEC

8:4 MUX

C in

Sum

Fig.2 4 Bit Binary to Excess-1 Code Converter with 8:4Mux The main function of MUX is to select the most possible output from the given two values. 8:4 MUX receives the values from the two operations such as RCA and BEC. First 4 bit addition has to be performed with RCA and the result outcome will be 4 bit. Second 4 bit has to be converted into 5-bit BEC. MUX will receive both 5bit and 4 bit RCA and generate 4 bit sum.

O/P

MU X

MU X

MU X

RESU LT RES ULT RESULT

Fig.3. 16 Bits Conventional Carry Select Adder (CSA)

For First 4 bit normal RCA addition has to be performed normally and with A+B+1 term to get most possible outputs. If the carry value is 0 then A+B is employed and if the value is 1 then A+B+1 is employed for the other sets of 4-bit addition. Then 0 has to be fed into second, third, and final 4- bit.After completing the first stage process 1 has to be fed for the same operation in the second stage. MUX will select the most possible output from the two stages and final sum can be calculated.MUX will select the first stage o/p only when the Cin is 0 and second stage o/p is selected when Cin is 1.

3.4 MODIFIED CARRY SELECT ADDER FOR 2n-2k-1

In the case of MCSA the use of and, or, not can be significantly reduced than compared to CSA. The second stag of operation implies the area reduction than compared to second stage of CSA. The entire operation is illustrated in below fig

A4 B4 A3 B3 A2 B2 A1 B1

0

0

0

FIRST 4BIT

SEC OND 4 BIT

4

3rd

BIT

FINAL BIT

0

TABLE.2.AREA UTILIZATION FOR 2n-2k-1

 Logic utilization used available utilization No of slice flip flop 29 1,536 1% No of 4 i/p LUT 115 1,536 7% No of bonded i/p 48 178 26%

From this table the area utilization for the proposed modulo has been significantly reduced based on several factors respectively.

5-BIT BEC

5-BIT BEC

5-BIT BEC

M M M

U U U

X X X

O/P R R R I/P

Fig.4. Modified Carry Select Adder (MCSA)

First 4 bits has to be taken and perform two additional operations with and without carry correction term. The carry correction term here is 15 because the value of k selected is 4. If the carry value is 0 then go for first case (A+B) then if the carry value is 1 then go for (A+B+T). Later 0 has to be fed into all the next 4 bits till the last for RCA operation. In the second stage 5-bit BEC has been implemented in order to reduce the extra addition in RCA.MUX will select the possible output from both the operations. In the first stage if the output is 0000.Then while employing BEC then the output becomes 00001 .Later during MUX operation if the Cin is 0 then 0000 is selected otherwise 00001 is selected .

TABLE.1. 4 BIT RCA TO 5 BIT BEC

 4 BIT RCA 5 BIT BEC 0000 00001 0010 00101 0011 00111

4. Results and Discussions

The area utilization synthesis for both the novel modulo 2n- 2k-1 and 2n-1 adder is illustrated in table 3 respectively. The area synthesis report for both the design modulo implies that 2n-2k-1adder consumes lesser area than compared to 2n-1 adder .The no of slices for the proposed design modulo has been illustrated in both table 2 respectively.

Fig.11 Simulation Using Model Sim

From the above simulation by generating a and b bits the following operations such as sum of two bits and the selection by using MUX operation and the final results are obtained respectively.

TABLE.3. Comparison of area between the design modulo 2n-2k-1 and 2n-1 adder

 Area utilization 2n-2k-1 2n-1 Totalequivalent gate count for design 1,478 3,110 JTAGgate count for IOB 2,352 2,400 Peak memory usage 163 MB 165MB

Hence table 3 illustrates the total area reduction for both the design modulo .

6. CONCLUSION

In this paper the design modulo for novel 2n-2k-1 is discussed and proved that the design modulo is more efficient than compared to existing design modulo 2n-1 respectively. However the speed and efficiency has also been simultaneously increased to make the process convenient. Therefore this design novel modulo is proved efficient to design any sort of adder architectures such as 32 bit and 64 bit respectively. The complete design is verified in VHDL. The basic design of RTL is verified using XILINX tool. . Hence the complete area utilization and optimization are illustrated using synthesis report and the final design is synthesized at SPARTAN-2 of 90nm technology. The reduced no of gates used in MCSA offers better area performance. In future BEC scheme can be illustrated in square root carry select adder to reduce area respectively.

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