DOI : 10.17577/IJERTCONV2IS08042
Jasna. K , Riyas. A. N, 2014, Design and Simulation of Low Voltage Low Power Comparator in 180nm CMOS Process, INTERNATIONAL JOURNAL OF ENGINEERING RESEARCH & TECHNOLOGY (IJERT) NCETET – 2014 (Volume 2 – Issue 08),
- Open Access
- Total Downloads : 10
- Authors : Jasna. K , Riyas. A. N
- Paper ID : IJERTCONV2IS08042
- Volume & Issue : NCETET – 2014 (Volume 2 – Issue 08)
- Published (First Online): 30-07-2018
- ISSN (Online) : 2278-0181
- Publisher Name : IJERT
- License:
This work is licensed under a Creative Commons Attribution 4.0 International License
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Design and Simulation of Low Voltage Low Power Comparator in 180nm CMOS Process