Comparison of Multipliers for VLSI Application

Comparison of Multipliers for VLSI Application

Chinthanai Selvi. S Vigneshwari Rajagopal

M.E -VLSI Design AP/ECE

Department of ECE Department of ECE

Parisutham Institute of Technology and Science Parisutham Institute of Technology and Science Thanjavur, Tamilnadu. Thanjavur, Tamilnadu.

Abstract Multipliers are very important component in Digital Signal Processing Systems and Embedded application. The performance of any multiplier will depend upon power, delay and area. Recent works in VLSI Design to reduce significant amount of Multipliers power consumption. Multipliers perform one of the most frequently arithmetic operations. This spurious switching activity can be mitigated by balancing internal paths through combination of architectural and transistor-level optimization techniques. In this paper, deals with comparison of different multipliers are done for low power requirement. The power management has become a great concern due to the increased usage of multimedia devices. Multipliers are the main sources of power consumption in these devices. The area and speed of the multiplier is an important issue, increment in speed results in large area consumption and vice versa.

Keywords Partial Products, Digital Signal Processing, Multiplicand, Multiplier, Booth Algorithm.

1. INTRODUCTION

   With the recent trends in increasing mobility and performance in small hand-held mobile communication and portable devices, among three thrust areas i.e speed, area and power, speed has become one of the significance in modern VLSI design. The objective of good multiplier to provide a physically compact high speed and low power consumption unit. Being a core part of arithmetic processing unit multipliers are in extremely high demand on its speed and low power consumption.

   To reduce significant power consumption of multiplier design it is a good direction to reduce number of operations thereby reducing a dynamic power which is a major part of total power dissipation. In the past considerable effort were put into designing multiplier in VLSI in this direction. Parallel multipliers are used to speed up the processors compared to serial multipliers

   performance energy efficient logic style is having crucial importance in VLSI circuits. Multiplication in hardware can be implemented in two ways either by using more hardware for achieving fast execution or by using less hardware and end up with slow execution [3]. Traditional hardware multiplication is performed in the same way multiplication is done by hand: partial products are computed, shifted appropriately, and summed. In this paper compare the performance of three multiplier structure like array multiplier, Booth multiplier and Wallace tree Multiplier. In all those technique

   Booth Algorithm having superior Performance Parameter. This algorithm can be slow if there are many partial products (i.e. many bits) because the output must wait until each sum is performed. Booths algorithm cuts the number of required partial products in half. This increases the speed by reducing the total number of partial product sums that must take place.

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   Multipliers perform one of the most frequently en er ns d al l

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      countered arithmetic op atio in igit signa processors

      (DSPs). For embedded applications, it has become essential to design more power-aware multipliers. The power aware of multipliers uses new technology called Multi precision which include some characteristics (i) non negligible silicon and power overhead,(ii)Performance and throughput reduction brought by the shut-down of parts of the circuit and/or use of reduced supply voltage and(iii) restriction and great margins to the operating condition versatility of the multiplier. High

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1. G. Eason, B. Noble, and I.N. Sneddon, On certain integrals of Lipschitz-Hankel type involving products of Bessel functions, Phil. Trans. Roy. Soc. London, vol. A247, pp. 529-551, April 1955. (references)

2. J. Clerk Maxwell, A Treatise on Electricity and Magnetism, 3rd ed., vol. 2. Oxford: Clarendon, 1892, pp.68-73.

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6. Y. Yorozu, M. Hirano, K. Oka, and Y. Tagawa, Electron spectroscopy studies on magneto-optical media and plastic substrate interface, IEEE Transl. J. Magn. Japan, vol. 2, pp. 740-741, August 1987 [Digests 9th Annual Conf. Magnetics Japan, p. 301, 1982].

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