Comparative Study of Space Vector Pulse Width Modulation based T-Type Three-level Inverter

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Comparative Study of Space Vector Pulse Width Modulation based T-Type Three-level Inverter

Saikat Majumdar Dept. of Electrical Engg. ISM DHANBAD, INDIA

Ravi Raushan Dept. of Electrical Engg. ISM DHANBAD, INDIA

Bidyut Mahato Dept. of Electrical Engg. ISM DHANBAD, INDIA

Kartick Chandra Jana Dept. of Electrical Engg ISM DHANBAD, INDIA

Parashuram Thakura Dept. of Electrical Engg. BIT Mesra, Ranchi, INDIA

Shio Kumar Singh Chief, Capability Development TATA STEEL, JAMSHEDPUR

AbstractA three-phase T-type three-level inverter configuration is demonstrated. Analysis of suggested three-level inverter has been presented. An improved three-level space vector pulse-width modulation technique, which utilize the state redundancies has been explained and verified over recommended three-level inverter and neutral point clamped inverter under linear range of operation. Modelling and simulation of T-type three-level inverter using presented space vector pulse width modulation is carried out in MATLAB/SIMULINK environment and results are presented. Proposed inverter is also compared with other configurations.

Keywords Space vector pulse width modulation; T-type Inverter; total harmonic distortion; multi-level inverter.

  1. INTRODUCTION

    Multilevel inverter (MLI) was first introduced by Baker and Bannister in the year 1975 [1-2]. It came after the limitations of two-level inverter such as higher total harmonic distortion (THD), high switching frequency, high dv/dt losses, higher commutation problem and higher rating devices. Multilevel inverter can produce any desired higher output voltage by incorporating small DC sources. Application of multilevel inverter includes industrial drive control, renewable energy system, HVDC, STATCOM etc. [3-7].

    Some early introduced multilevel inverters such as Cascaded H-bridge (CHB) [2], Neutral Point clamped (NPC)

    1. and Flying Capacitor (FC) [9] are termed as classical inverter due to.an extensive application in research and industries. A single cell of H-bridge inverter have a DC- source with four switches, combination of such cell can produce any output voltage level by cascading the cells. Of H- bridge inverter is popular for multilevel application with

      modulation techniques such as sinusoidal pulse width modulation (SPWM) [10-12], selective harmonic elimination [13-14], hybrid modulation methods [15-16] nearest level technique [17] have been proposed and analyzed depending of inverter configurations. Among the numerous pulse width modulation (PWM) techniques sinusoidal pulse width modulation and space vector pulse width modulation are most widely used modulation techniques. Space vector PWM [11, 18] enables the efficient use of DC voltages that smartly works with vector control hence contributes less THD, better power factor and less switching losses at higher frequencies.

      In this paper, analysis of three phase T-type inverter [19] configuration is done using a modified SVPWM as control strategy for providing switching pulses.

  2. THREE- LEVEL T-TYPE INVERTER Three-phase three-level inverter configuration for

    Cascaded H-bridge (CHB), Neutral Point Clamped (NPC)

    and Flying Capacitor is shown in Fig.1. Present work is focused on a three-phase T-type inverter having comparatively reduced number of switches as depicted in Fig.2. Each phase of the three-phase T-type inverter constitutes two IGBT switches and one bi-directional switch. The IGBT switches (Sx1 and Sx2) x= (a, b, c), and the bi- directional switch (Sx3) blocks only half of the DC-link voltage. Whereas, the neutral-point clamped (NPC) inverter uses two switches connected in series to block the full DC- link voltage. Thus the conduction losses of T-type inverter are considerably reduced compared to that of NPC inverter.

    photovoltaic (PV) as it require isolated sources. Larger number of DC source for higher level is the limitation for H- bridge multilevel inverter. An inverter where one DC source with extra diodes connected to the neutral point thus avoiding use of larger number of DC source as earlier and this structure named as neutral point clamped (NPC) inverter. Large number of Diode restricts the application of NPC with increase in

    Sa1

    VDC

    Sa4

    Sa3

    Sa2

    Sb1

    VDC

    Sb4

    Sb3

    Sb2

    Sc1

    VDC

    Sc4

    Sc3

    Sc2

    output voltage level. Flying capacitor inverter uses capacitors in place of diodes but the number of capacitors also limits it for higher level application.

    Synthesizing a nearly sinusoidal output voltage is accomplished using various switching methods. Numerous

    1. Three-level Cascaded H-Bridge

      VDC

      VDC

      2

      Da1

      D

      Sa1

      Sa2

      Da4

      Sa3

      Da3

      Db1

      Sb1

      Sb2

      Db4

      Sb3

      Db3

      Dc1

      Sc1

      Sc2

      Dc3

      Dc4

  3. PRINCIPLE OF OPERATION

    Each phase of three-level T-type inverter operates in three different modes and generates output voltage in three-levels.

    Mode-I: In this mode of three level T-type inverter, switch Sa1 is turned ON and the phase current flows through the switch Sa1 and the output voltage becomes 0.5 VDC.

    Mode-II: In this mode of three-level T-type inverter, switch Sa3 is turned ON and the phase current flows through

    VDC

    a2 Da5

    Db2

    Db5

    Dc2

    Sc3

    Dc5

    the switch Sa3

    and the output voltage becomes 0. In this mode

    2

    Sa4

    Da6

    Sb4

    Db6

    Sc4

    Dc6

    always two diodes conducts irrespective of the direction of current.

    Mode-III: In this mode of three-level T-type inverter, switch Sa2 is turned ON and the phase current flows through

    1. Three-level Neutral point clamped

      the switch Sa2 and the output voltage becomes -0.5 VDC.

      VDC

      VDC

      2

      VDC

      2

      Sa1

      Sa2

      Da4

      Sa3

      Da5

      Sa4

      Da3

      Sb1

      Sb2

      Db4

      Sb3

      Db5

      Sb4

      Db3

      Sc1

      Sc2

      Sc3 Sc4

      Dc3

      Dc4

      Dc5

      Vdc

      2

      Vdc

      2

      Da3

      Sa3

      Da6

      Sa1

      Da5

      Da4

      Sa2

      Da1

      Da2

      Da6

      Db6

      Dc6

      1. Mode-I.

      2. Three-level Flying capacitor

    Fig.1 Basic three-level inverter topology.

    Bidirectional switch in Fig.2 has only one IGBT switch and four diodes where two diodes connected in series for forward conduction and two of them used for blocking half of DC-link voltage.

    TABLE . 1. SWITCHING TABLE FOR PHASE-A THREE- PHASE T-TYPE MLI

    Vdc

    2

    Vdc

    2

    Da3

    Sa3

    Da6

    Sa1

    Da5

    Da4

    Sa2

    Da1

    Da2

    Sa1

    Sa3

    Sa2

    Output voltage

    ON

    OFF

    OFF

    0.5 VDC

    OFF

    ON

    OFF

    0

    OFF

    OFF

    ON

    – 0.5 VDC

    Sa1

    Sa3

    Sa2

    Output voltage

    ON

    OFF

    OFF

    0.5 VDC

    OFF

    ON

    OFF

    0

    OFF

    OFF

    ON

    – 0.5 VDC

    Vdc

    2

    1. Mode-II.

      Sa1

      Da1

      Three-phase T-type inverter generates three levels of output voltage of magnitude 0.5VDC, 0 and -0.5VDC with proper switching pulse. The switching table for Phase-A of T- type inverter is shown in table 1. A delay must be introduced between the switching of switches to avoid the short- circuiting of DC source.

      Vdc

      2

      Da3

      Sa3

      Da6

      Da5

      Da4

      S

      Da2

      Vdc

      2

      Sa1

      Da3 D

      Da1

      D

      Sb1

      D

      Db1 D

      Sc1

      D

      Dc1

      • a2

        • a5

          Sa3

          b3 b5

          Sb3

          c3 c5

          Sc3

    2. Mode-III.

    Fig.3. Modes of operations

    Keeping in mind the cost and efficiency of the overall

    Vdc

    2

    Da6

    Da4

    Sa2

    Db6

    Da2

    Db4

    Sb2

    Dc6

    Db2

    Dc4 Sc2

    Dc2

    given systems, our keen interest in the reliability is increasing. Thus most of the modern research works are conducted keeping in mind the reliability of efficient power conversions particularly in the area of fault diagnosis and

    Fig.2. Three-level T-type Inverter configuration.

    fault tolerant control strategy.

  4. CONTROL STRATEGY

    The Space Vector Pulse Width Modulation (SVPWM)

    The modulation index (Mi) depends on the magnitude of reference voltage Vref. The ideal relationship between modulation index Mi and Vref is defined as:

    schemes are developed to find the three nearest nodes on the

    voltage hexagon lattice with respect to the reference vector. The mathematical formulation of the early SVPWM were

    M 0.907Vref

    i 0.866VDC

    (5)

    complex, because the voltage hexagon lattice was used in the Cartesian co-ordinate system. The co-ordinates of the nodes on the lattice are fractional numbers, which made the node selection difficult. The idea was that the reference vector was transformed from the Cartesian co-ordinate system to the 60 degree co-ordinate system. The 60 degree co-ordinate system represents one sector on the lattice and its benefit is that the co-ordinates for the nodes can be represented as integers. Therefore determination of the nodes could be accomplished by simple rounding functions and integer calculation.

    In linear modulation region (0 Mi .907):

    Here a modified SVPWM technique is introduced for the three-phase three-level inverter. For a particular reference vector, the sector of operation (Pi) and the angle ( ) is

    determined by using equations (1) and (2), respectively.

    The location of reference vector in any particular triangle

    ( i) can be determined with the decomposition vector (Vr, Vr) of reference vector. According to NEAREST THREE VECTOR(NTV) method, every vertex of a triangle is considered as a switching vector and every switching vector is represented by many switching states for selected location in a particular triangle. For a three-level inverter there are 27 switching states (n3 states for an n-level inverter). The space vector pulse width modulation is determined by selecting and analyzing every switching state for the given triangle of their respective on-times. Every switching state is responsible for the significant performance of the inverter.

    The on-time is defined as Ts=Ta+Tb+Tc. The volt-sec equation time averaging is followed:

    VrefTs=VaTa+VbTb+VcTc (6)

    60

    60

    Pi int 1

    60

    60

    rem

    (1)

    (2)

    n axis

    [11 1]

    Where, is denoted as the angle of reference vector with respect to -axis,int and rem indictes the function for integer and remainder respectively. The SVPWM diagram is divided into six sectors and each sector has four triangle depicted in Fig.4 with corresponding switching states.

    4

    [00 1] [110] [10 1]

    2 Vref

    1

    [111] [0 11]

    axis

    [111] [1 1 1] [000] [111]

    3

    0 1 1

    100

    m axi

    [1 1 1] [110] [111]

    [010] [110]

    [111] [10 1]

    Vref

    Where, V

    ref

    Fig.5. Triangles in sector one.

    is the reference voltage and Ts

    is the PWM

    [111] [111] [011] [111] [111] [000] [100] [0 11]

    axis

    [111]

    time. Here, two active vectors (Va, Vb) and zero vector is used as Vc.

    For a three-level inverter time T , T , T are defined as:

    [10 1] [111] [001] [101] [111] [110]

    Ta Ts 1 2Mi sin

    a b c

    T T 2M sin

    Linear Mode

    b s i 1

    [111] [0 11] [111]

    3

    (7)

    Fig. 4 Space vector diagram of a three level inverter.

    T T 2M sin

    c s 1 i 3

    The reference voltage vector with magnitude Vref moves on a circular trajectory. The modulation index Mi can be controlled as the trajectory is laying inside the hexagon. The decomposition vector (Vr, Vr) of the reference voltage into – axis having 600 angle to each other, for an N-level inverter can be determined as

    2N 1Vref

  5. SWITCHING PATTERN GENERATIONS

    A variable switching-pattern has been developed for better harmonics. The seven-segment switching patterns can be applied for triangle (or space vectors) having less number of switching redundancy and nine-segment for higher number

    Vr

    3Vdc

    2 N 1V

    sin

    (3)

    of switching redundancy. Depending on the redundancies of the switching states at the vertices of the triangles seven

    Vr

    3Vdc

    ref sin

    3

    (4)

    segment and nine segment time division is distributed for the three-level inverter as shown in Fig. 6-7.

    SECTOR 1 4 :

    200

    [00 1] [10 1] [110] [10 1] [00 1]

    Ta

    Ta

    Tb

    Tc

    Tb

    Ta

    [00 1] [10 1] [110] [10 1] [00 1]

    Ta

    Ta

    Tb

    Tc

    Tb

    Ta

    [11 1]

    Va Vb

    [11 1]

    0

    -200

    Vab (V)

    Vab (V)

    0 0.02 0.04 0.05

    Mag (% of Fund.)

    Mag (% of Fund.)

    Time (s)

    Vc

    Tc

    4 2 2 2 2 2 4

    Ts

    Fig. 6 seven segment switching-diagram.

    Nine-segment switching pattern implementation is preferred to the seven-segment switching sequence, where redundancies of switching states are increased for triangle say

    1 and 2 . The switching pattern for the seven-segment and the nine-segment is shown in table II.

    SECTOR 1 2 :

    [0 1 1][00 1] [10 1] [100] [110] [100] [10 1] [00 1][0 1 1]

    Fundamental (50Hz) = 179.8 , THD= 21.36%

    10

    5

    0

    0 2000 4000 6000

    Frequency (Hz)

      1. Output voltage waveform and THD of T-type inverter with modlation index (Mi) =0.907 for seven segment implementation.

        Vab (V)

        Vab (V)

        200

        0

        -200

        0 0.02Time (s) 0.04 0.05

        Mag (% of Fund.)

        Mag (% of Fund.)

        Fundamental (50Hz) = 173.9 , THD= 30.30%

        Va

        Vb Vc

        T T T T T

        T T T T

        10

        5

        0

        0 2000 4000 6000

        Frequency (Hz)

        a c b a c

        a b c a

      2. Output voltage waveform and THD of NPC inverter with

        6 3 2 3 3 3 2 3 6

        Ts

        Fig.7. Nine-segment switching-diagram.

        TABLE II. SWITCHING SEQUENCE PATTERN OF FOUR TRIANGLES IN SECTOR ONE

        modulation index (Mi) =0.907 for seven segment implementation.

        Vab (V)

        Vab (V)

        100

        Seven Segmentation

        Nine Segmentation

        3 : 0 11 111

        10 1 100 10 1

        111 0 11

        1 : 1 1 1 0 1 1

        00 1 000 100

        000 00 1 0 1 1

        1 1 1

        4 : 00 1 10 1

        111 110 111

        10 1 00 1

        2 : 0 1 1 00 1

        10 1 100 110 100

        10 1 00 1 0 1 1

        Seven Segmentation

        Nine Segmentation

        3 : 0 11 111

        10 1 100 10 1

        111 0 11

        1 : 1 1 1 0 1 1

        00 1 000 100

        000 00 1 0 1 1

        1 1 1

        4 : 00 1 10 1

        111 110 111

        10 1 00 1

        2 : 0 1 1 00 1

        10 1 100 110 100

        10 1 00 1 0 1 1

        0

        -100

        0 0.01 0.02 0.03 0.04 0.05

        Mag (% of Fund.)

        Mag (% of Fund.)

        Time (s)

        Fund. (50Hz) = 81.63 , THD= 55.01%

        20

        10

        0

        0 2000 4000 6000

        Frequency (Hz)

  6. SIMULATION RESULTS

    Modified three-level space vector pulse width modulation technique is applied on T-type inverter and NPC and corresponding output voltage with total harmonic distortion is depicted in Fig. 5. It is observed that T-type inverter have relatively reduced THD than NPC. The benefit for T-type inverter is the requirement of number of switches which reduces the cost of the inverter and complexity of circuit. Table.3. represents the comparison of T-type with classical configuration for component count.

      1. Output voltage waveform and THD of T-type inverter with modulation index (Mi)=0.454 for nine segment

        implementation.

        Vab (V)

        Vab (V)

        100

        0

        -100

        0 0.01 0.02 0.03 0.04 0.05

        Time (s)

        1. L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, M. A. M. Prats, The age of multilevel converters arrives, IEEE Ind. Electron. Mag., vol. 2, pp. 2839, 2008.

        2. J. Wen, K. Ma. Smedley, Synthesis of multilevel converters based on single- and/or three-phase converter building blocks, IEEE Trans. Power Electron., vol. 23, pp. 12471256, 2008.

        3. B. Mahato, P.R. Thakura, and K.C. Jana, "Hardware Design and

        Mag (% of Fund.)

        Mag (% of Fund.)

        Fundamental (50Hz) = 79.49 , THD= 50.13%

        20

        10

        0

        0 2000 4000 6000

        Frequency (Hz)

      2. Output voltage waveform and THD of NPC inverter with modulation index (Mi)=0.454 for nine segment

    implementation.

    Fig.8. Output voltage waveform and THD for different modulation index (Mi).

    TABLE 3. COMPARISON OF THREE-PHASE MLIS WITH T-TYPE MLI.

    Inverter Type/ Number of Component

    CHB MLI

    (Symm.)

    NPC MLI

    FC MLI

    T-Type MLI

    IGBTS

    /MOSFETS

    12

    12

    12

    6

    Bidirectional controlled switches

    0

    0

    0

    3

    Diodes

    12

    18

    12

    18

    Separate Supply/DC link Capacitor

    3

    2

    2

    2

    Flying Capacitor

    0

    0

    3

    0

  7. CONCLUSION

The selection of T-type inverter is made based on the benefits of reduced component count in the multilevel than the classical multilevel inverters. A modified space vector pulse width modulation is modelled that proposed variable switching patterns by using seven-segment for space vectors having less number of switching redundancy and nine- segment for higher number of switching redundancy to reduce harmonics. The whole circuit is simulated using MATLAB/SIMULINK platform. The simulation results of line voltages of two different multilevel inverters are presented. It is observed that, for a T-type inverter, there is a significantly improved harmonic profile than the neutral point clamped inverter for the same voltage level.

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