- Open Access
- Total Downloads : 11
- Authors : Payel Chand, Nikhil Agarwal, Biswajit Baral
- Paper ID : IJERTCONV3IS25019
- Volume & Issue : NCRAEEE – 2015 (Volume 3 – Issue 25)
- Published (First Online): 30-07-2018
- ISSN (Online) : 2278-0181
- Publisher Name : IJERT
- License: This work is licensed under a Creative Commons Attribution 4.0 International License
Comparative Study of Gate Underlap and Overlap in Junction-less DG-MOSFET with High k-Spacer through Simulation
Payel Chand*, Nikhil Agarwal*, Biswajit Baral#
*Student, # Sr .Asst. Prof.
Department of Electronics and Communication Engineering Silicon Institute of Technology, Bhubaneswar, Odisha
AbstractIn this paper a comparative study is shown between gate underlap and gate overlap of Junction less Double Gate MOSFET with high k-spacer (HfO2). The impact of gate underlap and overlap on the DC and RF performance of JL- DG MOSFET is analyzed with the help of a numerical TCAD device simulator. We engage Transconductance (gm), Cut-Off Frequency (fT), Total capacitance (Cgg), Miller capacitance as the key figure of merits for the analysis. The results conclude that the device with gate underlap has the efficacy for the usage in analog/mixed signal System On Chip (SOC) application, whereas the higher frequency operating devices are better operated with overlap. Underlap is undesirable due to current degradation in ungated region where as in case of gate overlap we got a very good ION current.
KeywordsJunctionless Transitors, Overlap, Underlap, TCAD, Haufnium dioxide (HfO2)
Microelectronics industry has experienced tremendous progress in the last fifty years, especially with regard to the evolution of the products (i.e. integrated circuits) for better performances. So far, this considerable growth of the semi- conductor industry has been due to its technological capability to constantly miniaturize the elementary components of circuits, namely the MOSFET (metal-oxide- semiconductor field effect transistor), the basic building block of VLSI (very large scale integration) integrated circuits. However, the continuous decrease of the silicon surface in order to satisfy the famous Moore's Law has resulted in serious physical and technological limitations, mainly related to the gate oxide (SiO2) leakage currents, the large increase of parasitic short channel effects and the dramatic mobility reduction due to highly doped silicon substrates. Recently, we come across a device called Junction-less double-gate MOSFETs (JL-DGMOSFETs) that has been shown to be more optimal for ultra-low power circuit design due to the improved sub-threshold slope and the reduced leakage current compared to bulk CMOS. Transistors are becoming so tiny that it is becoming increasingly difficult to create high-quality junctions. In particular, it is very difficult to change the doping concentration of a material over distances shorter than about
10nm. Junction less transistors could therefore help chipmakers continue to make smaller devices.Here we are using JL-DG MOSFET with high k-spacer along with the concept of gate overlap and underlap. We use Hafnium dioxide as high k-spacer. The Analog/RF performance of this device has been analyzed here for comparison between underlap and overlap gate. This paper is organized as stated: section II highlights the various device structures, Section III provide the variation of DC, analog and RF performance parameter as a function of overlap and underlap gate with SiO2 as the gate dielectric, in section IV we draw the conclusions. An acknowledgment to our guide and the references used to illustrate this paper are also mentioned.
II . DEVICE STRUCTURE
The figures reveal 2- dimensional cross section view of a JL- DG-MOSFET considered in our study. The devices comprises of a uniform doping concentration of 1020 cm-3 all throughout the structure. The nominal transistor dimension is given as channel length (L) = 15nm, thickness of substrate materials (tsub) = 10mm and Effective Oxide Thickness (EOT) = 0.8 nm. 2-dimensional device simulations are performed for JL-DG-FET with SILVACO ATLAS. Fermi Dirac carrier statics hand on hand with conventional Drift Diffusion model is included in this simulation. Concentration Dependent Mobility Model (COMMOB), and Field Dependent Mobility Model (FLDMOB), Shockley- Read-Hall (SRH) recombination, Auger recombination model and Newton & Gummels numerical iteration are used in the mobility reduction, recombination characteristics and to solve differential equation in ATLAS respectively. In this study we have rescinded Quantum Mechanical Effect (QME) due to the fact that QMEs and Ballistic transport are significant for devices with feature size less than 10 nm.. The underlap and overlap gate structure are created by reducing 1nm from alignment or by extending 1nm from alignment respectively.
Fig. 1: 2-D cross sectional structure of Jl-DG-MOSFET with Si as substrate material, gate aligned,air as spacer.
Fig. 2: 2-D cross sectional structure of Jl-DG-MOSFET with Si as
. substrate material, gate overlap,HfO2 as k-spacer
Fig. 3: 2-D cross sectional structure of Jl-DG-MOSFET with Si as substrate material, gate underlap, HfO2 as k-spacer. The various comparison analysis are done in section III.
RESULTS & DISCUSSIONS
DC PERFORMANCE INVESTIGATION
Fig.4: Variation of Drain Current ID as a function of Gate-to- source voltage VGS for different channel length L=10nm, 15nm and 20nm with device parameter values VDS=0.2v, tSi=10nm and
tOX=0.8nm for gate underlap.
Fig.5: Variation of Drain Current ID as a function of Gate-to- source voltage VGS for different channel length L=10nm, 15nm and 20nm with device parameter values VDS=0.2v, tSi=10nm and
tOX=0.8nm for gate overlap.
By analysing the above graphs, we come to a conclusion that the gate overlap devices have good ION current as compared to gate underlap devices. Underlap is undesirable due to current degradation in ungated region .We also conclude that at 10nm channel, overlap device works better. Even after channel length downscaling, the device works better due to use of high k-spacer.
ANALOG PERFORMANCE INVESTIGATION
In this section, the analog performance parameters of a JL- DG-MOSFET with high k-spacer are evaluated. We use the
Transconductance (gm) as the key figure of merit for comparing underlap and overlap gate .
Fig. 6: Plot of variation of transconductance (gm) as a function of Drain current for Channel Length L=10nm with device parameter values VDS=0.2v, tSi=10nm and tOX=0.8nm.
The above figure shows gate underlap has a high transconductance as comparison to gate overlap. The basic challenge in analog/RF design lies in achieving a good balance between bandwidth and power efficiency of a circuit. Underlap S/D design suppresses short channel effects (SCEs) leading to improved gate controllability thus leading to higher gm as compared to overlap. The peak gm is reduced later on in the graph due to the additional series resistance of the wider spacer region.
3.2. RF PERFORMANCE INVESTIGATION
In this section we investigate the RF performance using 3 standard figure of merits such as: – (a) Cut-Off frequency (fT)
(b)Total capacitance(Cgg) (c) Miller capacitance.
Fig 7:Variation of Cut-off Frequency (ft ) as a function of drain current ID for different Channel Length L=10nm,15nm and 20nm with device parameter values VDS=0.2v,tSi=10nm and tOX=0.8nm
for underlap gate.
Fig 8:Variation of Cut-off Frequency (ft ) as a function of drain current ID for different Channel Length L=10nm,15nm and 20nm with device parameter values VDS=0.2v,tSi=10nm and tOX=0.8nm
for overlap gate.
Fig. 8 shows the variation of cut-off frequency fT as a function of ID. fT is demonstrating a 1/L2 dependency as gm proportional to1/L at the sub threshold region fT attains a lwer value and increases with ID until it reaches a maximum value at a specific gate bias. At the maximum point of fT ,gate to source/drain capacitance is minimum. As L increases fT decreases .Where as it is inverse in case of underlap in Fig 7.So overlap has a high cutoff frequency while downscaling.
Fig 9:Variation of Cgg as a function of drain current ID for Channel Length L=10nm with device parameter values VDS=0.2v,
tSi=10nm and tOX=0.8nm.
The above graph shows that the total capacitance is reduced in case of underlap to a great extent. The reduction in the internal fringing capacitance due to the underlap profile results in lowering of the gate capacitance, Cgg, by nearly 40% at lower current levels whereas at higher current levels Cgg is reduced by only 10%.
Fig 10:Variation of Cgs/Cgd as a function of drain current ID for Channel Length L=10nm with device parameter values VDS=0.2v,
tSi=10nm and tOX=0.8nm.
The above graph shows Underlap channel design also results in an improvement in gatetosource (Cgs) to gatetodrain (Cgd) capacitance ratio (Cgs/Cgd). A decrease in Cgs/Cgd ratio implies a loss of channel charge and the increase in parasitic feedback capacitance. It is well established that Cgs/Cgd is an important limiting factor for the RF
In this work, ability of Junctionless DG MOSFET with gate underlap and overlap concept ,to suppress SCEs, and to increase performance are investigated. Among various,JL- DG MOSFETs with K-spacer ,underlap DG provides reduced parasitic capacitance to a great extent along with good transconductance ,on the other hand Overlap gate shows higher cutoff frequency and good ION current. In near future Linearity study of Underlap and Overlap and their comparison can be done for further analysis. Better RF performance is obtained in overlap DG MOSFET. For low power dissipation and reduced heating effect underlap DG- MOSFET are the best, as we see reduced paracitic capacitance there. Overlap DG MOSFET can be used in Devices that require good Ion current.
REFERENCES Nilesh Parman, Twinkle solankia, "A comprehensive study of Junctionless Transistors," Recent Trends in Engineering and Technology, pp. 1- 5, May 2011.
performance of short channel MOSFETs . As shown in  A.Kranti, Rashmi, S.Burignat, "Analog/RF
Fig.10 the use of underlap channel architecture improves Cgs/Cgd ratio by 30% at high Ids due to an enhanced gate controllability.
Fig. 11: Variation of Cgd/Cgs as a function of VGS for Channel Length L=10nm and Comparison between underlap and overlap.
The above graph shows that the parasitic capacitance value or the miller capacitance ratio is reduced in case of underlap.
Performance of Sub-100nm SOI MOSFETs with Non Classical Gate-Source/Drain Underlap Channel Design," IEEE Trans ,SiRF 2010, pp. 45-48, 2010.
Antonio Gnadi, Elena Gnani, "Theory of Junctionless Nanowire FETs," IEEE Trans. On Electron Devices, vol. 58, no. 9, pp. 2903-2910, September 2011.
Bipul C.Paul, Aditya Bansal, "Underlap DG MOS for digital subthreshold operation," IEEE Trans on Electron Devices, vol. 53, no. 4, pp. 910-913, 2006.
Minjian Liu ,Ming Cai, "Effect of overlap and Source/Drain doping gradient on 10nm CMOS performance," IEEE Trans.on Electron Device, vol. 53, no. 12, pp. 3146-3149, 2006.
B. Baral, "Effect of gate length downscalling on RF
and analog performance of a Junctionless DG- MOSFET for Analog/mixed signals SOC applications," NANOCON, 2014.
Kalyan Koley,Arka Dutta, "Subthreshold Analog/RF performance enhancement of underlap DGFETs with high k-spacer for low power applications," IEEE Trans. on Electron Devices, vol. 60, no. 1, pp. 63-69, 2013.