Comparative Analysis of Noise, Power and Area of 4 Bit Braun Multiplier and Baugh Wooley Multiplier with Minimum Number of Transistors in 45nm Technology

Comparative Analysis of Noise, Power and Area of 4 Bit Braun Multiplier and Baugh Wooley Multiplier with Minimum Number of Transistors in 45nm Technology

Supriyo Srimani1 , Diptendu Kumar Kundu2, Saradindu Panda3 , Prof. Bansibadan Maji4

1. Department of Radio Physics and Electronics, Rajabazar Science College, Calcutta University, India

2, 3. Electronics and Telecommunication Department, Narula Institute of Technology, India

4. Professor & Head, Dept. of Electronics and Communication Engineering,NIT, Durgapur, India

Abstract A central processing unit needs a considerable amount of processing time in performing logical operations, arithmetic operations, particularly multiplication operations. Multiplication is one of the arithmetic operations which require substantially more number of hardware resources and processing time than addition and subtraction. A multiplier is consist of mainly AND gates and Full Adders. Now a days resources are an important factor in case of any design. Any design must have less number of resources as well as it must be power efficient, noise immune. This paper presents a new high speed and Power efficient 4-bit Braun Multiplier and 4 bit Baugh Wooley Multiplier with less number of CMOS transistors. The circuit diagram is tested in 0.045µm i.e. 45 nm Technology. All the designs have been designed in DSCH2. Also Noise, Power and Delay have been calculated in Tanner Spice-13 in 45nm Technology.

Keywords Braun Multiplier Baugh Wooley Multiplier, T- Spice, DSCH2,

1. INTRODUCTION

   Multiplication is one of the most important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their multipliers and adders [1]. High performance multiplier is the important part of the CPU and DSP.

   Multiplier is one of the most important parameter to determine the processors speed. So, designing of multipliers are essential in Very Large Scale Integration (VLSI) systems and Digital Signal Processing (DSP) architectures applications. The continuing decrease in feature size of CMOS circuits and increase in chip density have made power consumption a major concern in VLSI design. Different types of multipliers have been proposed earlier like Array Multiplier, Tree Multiplier, and Braun Multiplier. In this paper we proposed a new Low Power 4-bit Braun Multiplier. To design a multiplier it is necessary to design an AND gate and Full Adder circuit. The proposed high speed and Low Power 4-bit Braun Multiplier was done using Tanner tools in 45nm technology. The basic arithmetic operation is addition of binary digits, i.e. bits. A full adder is one that adds three bits; the third input is

   produced from a previous addition operation. These Adders can be implemented by using different logic families. In this paper Baugh Wooley Multiplier and Braun Multiplier has been described by minimum number of transistors. 3 transistor AND gates and simulation results has been shown similarly 8 transistor Full Adder and simulation results has been shown also. Next the information about implementation of Braun Multiplier and Baugh Wooley Multiplier and the simulation results for Braun Multiplier Baugh Wooley Multiplier is shown. We have measured power, area and noise and made a comparison of power, area and noise for Braun Multiplier and Baugh Wooley Multiplier.

2. AND GATE

   The AND gate is designed by 3 transistors (3T) where both the NMOS are connected in cross-coupled manner i.e. the gate of the first NMOS (A) is connected with the source of second NMOS and vice versa. The inputs are given to the gate of each NMOS. Both the drain of NMOS are sorted and connected with the drain of PMOS. The gate and source of the PMOS are connected to ground. When the input is 00 i.e. A=0 and B=0 the PMOS is ON but both the NMOS are off so the output becomes zero. When the input is 01 i.e. A=0 and B=1 the PMOS is ON so the output becomes zero and similarly for input10 the output becomes zero. In the case of input 11 i.e. A=1 and B=1 the PMOS is off but both the NMOS are ON and the output becomes high. Figure.1 shows the circuit arrangement and the output waveform of the 3T AND Gate.

   Figure 1: Circuit Diagram and Output waveform of 3T -AND gate

3. FULL ADDER

   The design of an eight transistor (8T) full adder using XOR (3T) function and the waveform of Full Adder (8T) is shown in Figure.2. 8T full adder using centralizer output condition contains three modulesTwo XOR (3T) gates and one multiplexer (2T). The MUX is controlled by the output of XOR of the first two inputs. The 3T XOR operation is as follows: When the input B is at logic high, the circuit functions like a normal inverter. When the input B is at logic low, the CMOS inverter output is at high impedance. However, the pass transistor M3 is enabled and the output Y gets the same logic value as input A. However, when A=1 and B=0, voltage degradation due to threshold drop occurs across pass transistor and consequently the output Y is degraded with respect to the input.

   Figure 2: Circuit Diagram and Output waveform of 8T Full Adder

4. BRAUN MULTIPLIER

   Braun multipliers are regularly arranged arrays that have n (n-

   1) adders and n2 AND gates, where n is the number of inputs. Each of the inputs A and B of the multiplier cells product bits is generated in parallel with the AND gates. The partial products can be added to the previous sum of the partial product by using one row of an adder. The carry signals are shifted one bit to the left and then added to the sums of the first adder and the new partial product. They are then passed diagonally downward to the next adder stage. There is no horizontal carry propagation for the first rows. Instead, the carry bit is saved for the subsequent adder stage.

   Consider the multiplication of two unsigned n-bit numbers, where

   A an1 an2 …….a0 is the multiplicand and

   B bn1 bn2 …….b0 is the multiplier.

   The product P pn1 pn2 …….p0 can be written as

   Figure 3: Circuit Diagram and of 4 bit Braun Multiplier

   Figure 4: Tanner Spice Diagram and of 4 bit Braun Multiplier

5. BAUGH WOOLEY MULTIPLIER

   Baugh Wooley Twos compliment Signed multipliers is the best known algorithm for signed multiplication because it maximizes the regularity of the multiplier and allow all the partial products to have positive sign bits. Baugh Wooley Multiplier is used for both unsigned and signed number multiplication. Signed Number operands which are represented in 2s complemented form. Partial Products are adjusted such that negative sign move to last step, which in turn maximize the regularity of the multiplication array. Baugh Wooley Multiplier operates on signed operands with

   i

   j

   follows: P n1 n1 a a

   i0 j 0

   2i j

   2s complement representation to make sure that the signs of all partial products are positive. The basic blocks are constructed by Grey Cell and White cell, which are given in

   The Circuit diagram of 4 bit Braun Multiplier is shown in Figure 3 where the lighter shade of grey denotes the AND gates and the darker shades denotes The Full Adder. Figure 4 shows the T-Spice diagram of the multiplier.

   Figure 5. In case of White Cell a AND gate and a Full Adder is used and in case of Grey Cell the AND gate is replaced by a NAND Gate. The Circuit diagram of 4 bit Braun Multiplier is shown in Figure 6 where the shade of grey denotes the Grey Cells and the similar cells are white coloured are White Cells.

   The Full Adders are shon by lighter grey shade. Figure 7 shows the T-Spice diagram of the multiplier.

   Figure 5: White Cell and Grey Cell

   Figure 6: Circuit Diagram and of 4 bit Baugh Wooley Multiplier

   Figure 7: Tanner Spice Diagram and of 4 bit Baugh Wooley Multiplier

6. RESULT ANALYSIS

   The circuit of 4×4 Braun Multiplier and Baugh Wooley Multiplier has been tested in DSCH2. The Noise, Power has been simulated in Tanner Spice-13 in 45nm Technology. The input voltage is taken as 0.5V. The frequency of operation is taken as 1000MHz. The Comparison table of Noise, Power, Area and Transistor count of 4×4 Braun Multiplier and Baugh Wooley Multiplier is given in Table 1.

   Figure 8: Output Waveform of 4 bit Braun Multiplier

   Figure 8: Output Waveform of 4 bit Baugh Wooley Multiplier

   Table 1: Comparison between Different Multipliers

   	Braun Multiplier	Baugh Wooley Multiplier
   Noise (µV)	250	300
   Power Consumption	1e-012	5.571e-012
   Area	7.5mm2	7.8mm2
   Transistor Count	144	214

7. CONCLUSION

In modern technology, it is very necessary for any design, is low power consumption to make it more efficient and cost effective. Here we design the 4 bit Baugh Wooley and Braun multiplier with less number of transistors rather than existing type. Reduction in number of Transistor means minimizing the Power consumption and Area. Moreover in developing and DSP processor or embedded processor, if the blocks are designed with our design, the design may be more efficient. Al last here we also make a comparison between our two designs and the conventional multiplier design to reach the conclusion that our both design are more efficient than other conventional design.

REFERENCES

1. Sumit Vaidya, and Deepak Dandekar DELAY-POWER PERFORMANCE COMPARISON OF MULTIPLIERS IN VLSI CIRCUIT DESIGN, International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, July 2010

2. P.S.H.S.Lakshmi, S.Rama Krishna, K.Chaitanya, A Novel Approach for High Speed and Low Power 4-Bit Multiplier, IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) ISSN: 2319 4200, ISBN No. : 2319 4197 Volume 1, Issue 3 (Nov. – Dec. 2012), PP 13-26

3. Abhijit Asati, Chandrashekhar An Improved High Speed fully pipelined 500 MHz 8.8 Baugh Wooley Multiplier design using 0.6 m CMOS TSPC Logic Design Style 2008 IEEE Region 10 Colloquium and the Third ICIIS, Kharagpur, INDIA December 8-10.

4. Abhishek Mukherjee, Abhijit Asati Generic Modified Baugh Wooley Multiplier 2013 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2013]

5. Jin-Hao Tu and Lan-Da Van Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh Wooley Multipliers IEEE TRANSACTIONS ON COMPUTERS, VOL. 58, NO. 10, OCTOBER 2009