Cascaded H-bridge 5-level Inverter on Hybrid PWM Technique with Voltage Boosting Ability

DOI : 10.17577/IJERTV3IS071375

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Cascaded H-bridge 5-level Inverter on Hybrid PWM Technique with Voltage Boosting Ability

Ashok Kumar Patel

Dept. of Electrical Engineering SATI, Vidisha

Madhya Pradesh, India

S. S. Thakur

Assistant Professor Dept. of Electrical Engineering

SATI, Vidisha Madhya Pradesh, India

  1. P. Phulambrikar, Associate Professor & HOD Dept. of Electrical Engineering

    SATI, Vidisha Madhya Pradesh, India

    Abstract- Cascaded H-bridge MLI is most efficient topology for medium and high voltage DC-AC conversion, having less output harmonics and less commutation losses. Disadvantages is their complexity, more no. of power devices, passive components and a complex control circuitry. This paper focus on single phase 5 level inverter with characteristics like output voltage boosting ability along with capacitor voltage control. The proposed topology uses CHB with bidirectional switches and 4 auxiliary switches producing boost up output voltage. Here a hybrid PWM technique is applied to control the power devices. There is comparative study between CHB and proposed topology between number of power devices used and THD. THD of proposed topology is reduced and analyzed by FFT window. The result are simulated by MATLAB/SIMULINK software.

    Keywords – Multilevel Inverter(MLI), CHB, Hybrid PWM, Cascaded Neutral point clamped Inverter.

    1. INTRODUCTION

      In today's era there is demand of high power equipment which can develop the Megawatt level. Inverter is a device which converts DC- AC voltage. Multilevel inverter gives 3 or more level in the output voltage[1]. MLI are basically 3 types i.e. Diode clamped inverter, Capacitor clamped inverter and Cascaded H-bridge inverter[2]. Cascaded H- bridge(CHB) inverter is more superior among all of the above. In MLI there is less dv/dt stress, improved output voltages, smaller filter size, reduced EMI and lower total harmonic distortion(THD). Cascaded MLI basically consists of many identical H-bridge cells connected in series from output side[2]. The cascaded inverter may further be classified as Symmetrical and Asymmetrical inverter based on voltage sources[9]. In symmetrical, the DC bus voltage is same & in Asymmetrical the DC bus voltage is different. The symmetrical CHB is more beneficial over Asymmetrical CHB with respect to modularity, maintenance and cost. In

      case of Asymmetrical CHB as per voltage requirement the DC bus voltage is varied but in case of symmetrical CHB without varying the DC bus voltage, the voltage level cab be increased. This topology provides provision to achieve increased output level by taking different voltage levels from series stacked capacitors. In this paper a paper a single phase

      5 level inverter which consists of cascaded H-bridge, bidirectional switch and auxiliary circuit which boost up the voltage level. In bidirectional switch there is 4 diode and an IGBT. There is 2 capacitors which is used to store the energy

      , connected parallel to bidirectional switch[3]-[4]. In this paper a new configuration of (symmetrical H-bridge) single phase 5 level inverter is lodged which produces a 5 level output instead of 3 level as in case of conventional H-bridge. It also produces boost output voltage compared to conventional H-bridge topology which have 2 H-bridge cells producing 5 level output voltage but output voltage is equal to input DC voltage. In this proposed topology the boost voltage is twice the input DC voltage .

    2. PROPOSED CONVERTER TOPOLOGY

      The basic principle of proposed topology is that there is 5 level output voltage by single phase multilevel inverter i.e. (2V, V, 0 ,-V, -2V)AC voltage. By proper switching technique these output can be achieved easily. The proposed topology is given here in fig 3. There is total 9 IGBT switches, 4 main bridge switches, 1 bidirectional switch including 4 diodes and 4 auxiliary switches connected to DC voltage source. The auxiliary switches helps in boosting the voltage level. The H-bridge switches are s1, s2, s3, s4 and other sa1, sa2, sa3, sa4 are auxiliary connected across same leg which plays a role in boosting the voltage. Input DC source the positive terminal between sa1 and sa2 and negative terminal between switches sa3 and sa4. The

      capacitor C1 and C2 are divided as capacitor voltage[7]. The conventional H-bridge for 3 level and 5 level are shown in fig 1 and fig2.

      Fig 1: Conventional H-bridge Inverter

      Fig 2 : Cascaded H-bridge Inverter

      Fig 3 : Proposed Multilevel Inverter.

    3. OPERATION OF PROPOSED TOPOLOGY

      Here how the 5 level output is achieved by new topology is explained.

      The maximum positive voltage i.e. 2V is achieved when the s1 and s2 are conducting, connecting to the load terminal and V is obtained when sa1, BD, s2, sa4 gets turned ON and remaining OFF.

      The maximum negative output voltage i.e. -2V is achieved when s3 , s4 are conducting connected to load terminal here current flows in reverse direction across the load and -V is obtained when sa1, sa3, BD, s3 are turned ON and remaining are OFF.

      The overall operation of new topology can also be understand by lookup table which is given in below table. Here 0 means switches are OFF and 1 means switches are ON.

      Table for Proposed Multilevel Inverter Switching:

      Voltage

      level

      +2V

      +V

      0

      -V

      -2V

      aa1

      0

      0

      0

      1

      0

      aa2

      0

      1

      0

      0

      0

      BD

      0

      1

      0

      1

      0

      A1

      1

      1

      0

      0

      0

      A2

      0

      0

      1

      1

      1

      A3

      1

      0

      1

      0

      0

      A4

      0

      0

      0

      0

      1

    4. PWM CONTROL SCHEME

      A stair case waveform of MLI is obtained by using PWM modulation technique to get controlled output voltage[1]. There are many modulation techniques available among them PWM is most efficient. The PWM is further divide as single pulse PWM, space vector PWM, hybrid PWM, phase displacement control[1]. Here we are using hybrid based PWM control scheme[6],[8]. Sinusoidal signal having 50Hz frequency and by using repeating sequence we generated the reference signal and finally compared with carrier signal which are triangular wave which is shown in fig 4. The modulation index is 0.61.

      The modulation index, M is defined as M = 1/2( / )

      where is amplitude of voltage reference and is amplitude of the voltage carrier signal.

      This benefit of this scheme offers the charge balance control in the DC source and voltage across capacitors are shown in fig 9 which are in same magnitude.

      Fig 4: Modulation Technique used for Proposed Inverter

      Fig 5: Switching pulses for A1 and A2

      Fig 6: Switching pulses for A3 and A4

    5. CAMPARISON OF PROPOSED MLI WITH CONVENTIONAL H-BRIDGE TOPOLOGY

      The new concept of 5 level MLI uses 9 switches out of which 4 switches i.e. s1, s2, s3 ,s4 are creating conventional H-bridge they are main conducting switches with the help of bidirectional switches BD. It givs 5 level output voltage and

      remaining are auxiliary switches. The new configuration have reduced components which are shown in table.

      Multilevel Inverter

      Number of Conducting Switches

      Number of Auxiliary Switches

      Number of Capacitors

      Number of Diodes

      Proposed Inverter

      8

      1

      2

      12

      Conventional H-Bridge

      8

      0

      0

      8

      Diode Clamped

      8

      0

      4

      20

      Capacitor Clamped

      8

      0

      10

      8

      Fig 7 : 5 level single phase output of cascaded H-bridge Inverter

      Fig 8: 5 level single phase output of Proposed Inverter

      Selected signal: 4 cycles. FFT window (in red): 4 cycles

      100

      0

      -100

      0

      0.01 0.02 0.03

      0.04

      Time (s)

      0.05 0.06 0.07 0.08

      5

      4.5

      Mag (% of Fundamental)

      4

      3.5

      3

      2.5

      2

      Fundamental (50Hz) = 200.3 , THD= 19.55%

      Fig 9 : Voltage across Capacitors C1 & C2

      The percentage of components reduced with respect to new topology is given as

      Diode = 60% (8 instead of 20)

      Capacitor = 50% (2 instead of 4) with

      diode clamped

      Capacitor = 80% (2 instead of 10) with

      flying capacitor clamped configuration.

      1.5

      1

      0.5

      0

      0 200 400 600 800 1000 1200 1400 1600 1800 2000

      Frequency (Hz)

      Fig 11: FFT window for Cascaded H-bridge Multilevel inverter

      Selected signal: 4 cycles. FFT window (in red): 3 cycles

      200

      100

      0

      -100

      -200

      0 0.01 0.02 0.03

      0.04

      Time (s)

      0.05 0.06 0.07 0.08

      Selected signal: 4 cycles. FFT window (in red): 4 cycles

      Fundamental (50Hz) = 311.4 , THD= 9.12%

      7

      100

      6

      0

      Mag (% of Fundamental)

      5

      -100

      4

      0.05 0.06 0.07 0.08

      0.04

      Time (s)

      0.01 0.02 0.03

      0

      3

      2

      Fundamental (50Hz) = 149.1 , THD= 39.61% 1

      35

      0

      30 0 200 400 600 800 1000 1200 1400 1600 1800 2000

      Frequency (Hz)

      Mag (% of Fundamental)

      25

      20

      15

      10

      5

      0

      0 200 400 600 800 1000 1200 1400 1600 1800 2000

      Frequency (Hz)

      Fig 10: FFT window for Conventional H- bridge Multilevel Inverter

      Fig 12: FFT window for Proposed Multilevel Inverter.

      In case CHB, 2 separate voltage sources are required for getting 5 level output voltage. In proposed topology there is an extra switch than the CHB inverter for 5 level output voltage. In this topology we uses only 1 single DC voltage source whereas in CHB there is 2 voltage sources to produce 5 level output voltage. In the proposed topology input DC source is 150V and output AC voltage is 300V. In proposed method the Total Harmonic Disorder(THD) is also reduced to minimum level. There is comparison of THD between all methods discussed in this paper , shown in given table:

      Table for Total Harmonic Distortion(THD) comparison between topologies.

      Inerter

      Total Harmonic Distortion (THD) %

      Convectional H-bridge

      39.61

      Cascaded Multilevel Inverter

      19.55

      Proposed Inverter

      9.12

    6. CONCLUSION

The proposed topology for single phase 5 level inverter is much better than the cascaded H-bridge single phase inverter in terms of voltage level, total harmonic distortion(THD), DC voltage source. It uses an extra auxiliary unit and 2 capacitors as compared to CHB. The main feature of this topology is that it requires half input DC voltage than the CHB inverter. As compared to other topology it has minimum THD.

REFERENCES

  1. Rashid, M. H, 2004. "Power electronics: Circuits, devices and applications". Third Edition, Prentice Hall.

  2. J. Rodriguez, J. S. Lai, and F. Z. Peng, "Multilevel inverters: A survey of topologies, controls and applications," Industrial Electronics, IEEE Trans. Ind. Electronics, vol. 49, no. 4, pp. 724-738, 2009.

  3. Ebrahim Babaei, 2008, "A Cascaded Multilevel Converter Topology with Reduced Number of Switches" IEEE Transactions on power electronics, Vol. 23, No. 6.

  4. L. M. Tolbert, F. Z. Peng, T.G. Habelter, " Multilevel PWM methods at low modulation indices" IEEE Transactions on power electronics, vol. 15, No. 4, July 2000, pp. 719-725.

  5. Gupta, Krishna Kumar, Jain Shailendra, "A novel universal control scheme for multilevel inverters," Power electronics, machines and drives(PEMD 2012), 6th International Conference on, vol., no., pp. 1-6, 27-29 March 2012.

  6. Rahim, Nasudin A., Selvaraj Jeyray, "Multistring Five-level Inverter with Novel PWM Control Scheme for PV Application," IEEE Transaction on Industrial Electronics, vol. 57, no. 6, June 2010.

  7. Singh P., Tiwari, S., "A New Transistor Clamped 5-

    level H-bridge Multilevel Inverter with Voltage Boosting Capacity," IEEE Transaction on Power Electronics, Drives and Energy System(PEDES), 2012 international Conference on 16-19 Dec 2012.

  8. M. Thirumalai, V. Prakash, "Design and Implementation of Hybrid Multilevel Inverter for High Output Efficiency," International Conference on Smart Structures & System (ICSSS- 2013), March 28-29, 2013, Chennai, India.

  9. Bharatkar, S.S.; Bhoyar, R.R.; Khadtare, S.A., "Analysis of Three Phase Cascaded H-Bridge Multilevel Inverter For Symmetrical & Asymmetrical Configuration," IEEE Transaction on Automation, Control, Energy & Sysytems(ACES), 2014 First International Conference on 1-2 Feb 2014.

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