# Cascaded 13 Level Inverter using Series Connection of SubMultilevel Inverters

Text Only Version

#### Cascaded 13 Level Inverter using Series Connection of SubMultilevel Inverters

1

ICESMART-2015 Conference Proceedings

 State Switch es states Vo S1 s; S 2 s; … s ,2 s ,,,2 s <,,+2>12 s ;,,+2)12 1 1 1 0 0 … 0 0 0 0 0 2 0 I I 0 … 0 0 0 0 V "' 3 0 0 I I … 0 0 0 0 2Vd c … n – 1 0 0 0 0 … 1 1 0 0 (n – 2)Â¥c'., n 0 0 0 0 .. . 0 1 0 I (n- l )Vdc n – I 0 0 0 0 … 0 0 1 l nV c1c
 State Switch es states Vo S1 s; S 2 s; … s ,2 s ,,,2 s <,,+2>12 s ;,,+2)12 1 1 1 0 0 … 0 0 0 0 0 2 0 I I 0 … 0 0 0 0 V "' 3 0 0 I I … 0 0 0 0 2Vd c … n – 1 0 0 0 0 … 1 1 0 0 (n – 2)Â¥c'., n 0 0 0 0 .. . 0 1 0 I (n- l )Vdc n – I 0 0 0 0 … 0 0 1 l nV c1c

1. PROPOSED GENERALIZED MULTILEVEL

INVERTER

1. Proposed Submultilevel Inverter

v 1 S' , ,

Table 1. Output voltages for states of switches

2. Proposed Generalized Multilevel Inverter

, dle 's n t i S2 s,

I —-

(n-+ 2-) / 2 –' ——- … _

Fig 1. Proposed generalized submultilevel inverter.

To achieve the desired voltage and number of voltage levels The proposed submultilevel inverters is connected in series.

Fig 1 shows the proposed sub multilevel inverter. As in Fig 1, the topology consists of n de voltage sources. In general, de voltage sources can have the different values. However, to have equal voltage steps, de voltage sources are considered to be the same and equal to Vdc. Each SMI consists of n + 2 number switches. Some of the switches in the circuit are unidirectional and the others are bidirectional. The unidirectional switche consist of an insulated gate bipolar transistor with diode connected antiparallel to it. The switches Sl, S_ 1 , S(n+2)/2 , and S_ (n+2)/2 are unidirectional and all other switches are bidirectional; hence, they have to be both positive and negative voltages. For instance, when S(n+2)/2 is

turned ON, voltage Vdc is on the switch Sn/2 , and if the switch S(n- 2)/2 is turned ON, the voltage equal to – Vdc is on

turned ON, voltage Vdc is on the switch Sn/2 , and if the switch S(n- 2)/2 is turned ON, the voltage equal to – Vdc is on

Fig 2 shows m submultilevel inverters connected in series. Each SMI has n number of de voltage source. The de voltage source in each SMI are equal. The output voltage of the SMI are always positive or zero. It is necessary to change the voltage polarity in every half cycle to operate as an inverter. For this purpose an H-bridge inverter is added to the output of the series connected SMI. It is important to note that the switches of the H-bridge must have higher voltage. This is to be considered in the design of the inverter. However, switches are turned ON and OFF once during a fundamental frequency cycle. hence, these switches would be high-voltage lowÂ­ frequency switches.

#### iP;opo ed ;ubsyste, -…..-.,..v.

-0 1

-0 1

-,-Â·- -t -T-.,—-,rI

-,-Â·- -t -T-.,—-,rI

2

2

the switch Sn/2 . The same conditions are applicable for the 1

other switches. Hence, the switches have to be both positive

conduct the backward current that is as a result of inductive I

2s s a e-

__________ ., ! 3 I 4I

__________ ., ! 3 I 4I

:n:t :_

.. \

J : o, V 0

and the negative voltages. In addition, the switches should

characteristics of the load. Therefore, It can be concluded that the switches must be bidirectional. There are some circuit configurations for bidirectional switches. The common emitter topology is used in this topology because it needs one gate driver for a switch. Looking at the types of the switches, 2n IGBTs are required in the following SMI. The number of the antiparallel diodes is equal to the number ofIGBTs .

The proposed SMI can only generate zero and positive voltage levels. The zero output voltage is obtained when both the switches are turned ON at same instant. proper switching between the switches can generate other voltage levels. Table I shows the different states of the switches for each output voltage value. In this table, 1 means that the switch is turned ON and O indicates that the switch is in OFF state.

Considering Fig. 1, for each value of the output voltage of SMI, two switches must be turned ON, one from the lower switches and the other one from the upper switches of the circuit. For example, to get output voltage of Vdc, the switches S_l and S2 are turned ON. the switches Sn/2 and S_ (n+2 )/2 should be turned ON in order to obtain the output voltage of (n – l)Vdc.

:-P;opo-;ed ;ubsyste

r———"'—-.J

1 Proposed subsystem 1 v r r

mth stage I : o,m _ .

Fig 2. Proposed general multilevel inverter using series connection of m

proposed SMI, each one has n de voltage sources.

2. SIMULATION RESULTS

For the simulation the load is an R load with the value of 45 Q . The output voltage frequency is assumed 50 Hz. There are many other control methods used for multilevel inverter. It can be observed that the staircase control method is used in this multilevel inverter. The term staircase control method is used to state that in this method, transition from one level to the other level happens once. This control method tends to generate a staircase voltage which minimizes the error with respect to the reference voltage.

::

——

Â·-

,.

——

Â·-

,.

ICESMART-2015 Conference Proceedings

…… …… ………………………o………………………………………

tc:ftÂ· ,!…j

…… …… ………………………o………………………………………

tc:ftÂ· ,!…j

—,'C-,—–,'– —,'C-,– — c-,– — c-,– — c-,—–,'

0 0.01 0.02 0.03 0.04 005 0.06 0.07 0.08 0.09 0.1

Time (s)

Fundamental (50Hz) = 128.5 , nm= 12.52%

—,'C-,—–,'– —,'C-,– — c-,– — c-,– — c-,—–,'

0 0.01 0.02 0.03 0.04 005 0.06 0.07 0.08 0.09 0.1

Time (s)

Fundamental (50Hz) = 128.5 , nm= 12.52%

rrÂ·Â· Â·Â·:Â·Â·Â·Â· -Â·Â·;:Â·Â·

50

0

.50

,.

,.

– f FTonatys

– f FTonatys

Selected sigflal: 5cycles. FFTwindow{in red): 1 cycles

lOV 20V 40V 80V

Fig. 3. Thirteen-level inverter based on the proposed Asymmetric topology with n = l and m = 4.

Fig. 3 shows the 13-level inverter based on the proposed symmetric multilevel inverter with n=l. Four de voltage sources 90V, 45V ,23V ,12.5V have been used so that the maximum output voltage will be 170V. The number of IGBTs

12

i 0.8

Â§

… 0.6

f o.4

0.2

Fig 6. Total harmonic distortion

1000

for a 13-level inverter in the proposed topology is 12.

Fig 4. Schematic of thirteen level inverter.

t ITTIID ,"J:1111

Fig 6 shows the total harmonic distortion The proposed topology has the advantage of its reduced number switches and harmonics are reduced with THD value of 12.52 at 128.5V is achieved. For proposed harmonic spectrum of the simulation system is as shown in the fig.4, which shows the results are well within the specified limits of IEEE standards. The results of both output voltage and FFT analysis are verified by simulating the main circuit using MATLAB.

3. CONCLUSION

A multilevel inverter with individual de sources has been proposed for use in large electric drives. Simulation results have shown that with the control strategy operates the switches at the fundamental frequency, the converters have low output voltage, Total Harmonic Distortion(THD), high efficacy and power factor.

Simulation has been done in the MATLAB /SIMULINK. From the simulation it is noted that new MLI topology works well and shows hope to reduce the cost and complexity.

\

\

/ 1'] 110 1 \

/ \ I

1

I

I

t'rm "1 . l .. 11

\

\

I

Whenever the output voltage levels gets increased, the number

I 1 /

I

r of switches will be used is very less compared to other

Â·11 I

\ " 1' \ i'

/ \\J I

i' \I

multilevel topologies. By the increase in output voltage levels

! 11:11' 111 11111

Â·

\ 1111111

I I

11 11

the total harmonic distortion starts get reduced, so that it can be used in many power applications.

, 01111

I I

/ m'1, 11Â£n11

1 1111 \ /..\.

',

',

\

\

/ \I

ID II

// \,

/ \ ,r

REFERENCES

1, I

.

",../

\

\

Ii '

' I I UJJ" \

1'

lilll.'

.1

I,  J. Rodriguez, J. S. Lai, and F. Z. Peng, "Multilevel inverters: A survey of

I

I

I I \,,1111 \i

Fig 5 output voltage of thirteen level

Fig 5 shows the output voltage of the cascaded submultilevel inverters. The polarity of the voltage is changed using the HÂ­ bridge connected to the output of the submultilevel inverters. In the test condition (R = 45, Vo,max = 100 V), the power loss of the proposed multilevel inverter, shown in Fig. 5, is about 12W. However, the power loss of the asymmetric CHB topology with the same conditions (with the same value of voltage and load) is about 15.5 W. It can be as a result of the fact that in the following topology less semiconductor devices are in the current path in any instant of time in comparison with the asymmetric CHB topology. In this condition, active output power of the inverter is about 217 W.

topologies, controls, and applications," IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724-738, Aug. 2002.

1. J. H. Kim, S. K. Sul, and P. N. Enjeti, "A carrier-based PWM method with optimal switching sequence for a multilevel four-leg voltage-source inverter," IEEE Trans. Ind. Appl., vol. 44, no. 4, pp. 1239- 1248, Jul./Aug. 2008.

2. 0. Lopez, J. Alvarez, J. Doval-Gandoy, F. D. Freijedo, A. Nogueiras, A. Lago, and C. M. Penalver, "Comparison of the FPGA implementation of two multilevel space vector PWM algorithms," IEEE Trans. Ind. Electron., vol. 55, no. 4, pp. 1537- 1547, Apr. 2008.

3. A. A. Boora, A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, "Voltagesharing converter to supply single-phase asymmetrical fourÂ­ level diode clamped inverter with high power factor loads," IEEE Trans. Power Electron., vol. 25, no. IO, pp. 2507- 2520, Oct. 2010.

4. J. Rodriguez, S. Bernet, P. Steimer, and I. Lizama, "A survey on neutral point clamped inverters," IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2219-2230, Jul. 2010.

4