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**Authors :**Pavan Kumar R, S. Shridevi -
**Paper ID :**IJERTCONV2IS13042 -
**Volume & Issue :**NCRTS – 2014 (Volume 2 – Issue 13) -
**Published (First Online):**30-07-2018 -
**ISSN (Online) :**2278-0181 -
**Publisher Name :**IJERT -
**License:**This work is licensed under a Creative Commons Attribution 4.0 International License

#### Area and Power Optimization of Chaotic Oscillator Using RK4 Method

Pavan Kumar R1

Department of ECE, CMRIT Visvesvaraya Technological University Belgaum, Karnataka pavankrnaik@gmail.com

S. Shridevi2

Asst. prof. Department of ECE, CMRIT Visvesvaraya Technological University Belgaum, Karnataka sridevi.s@cmrit.ac.in

Abstract Chaos theory studies the behavior of dynamical systems that are highly sensitive to initial conditions. Discretization of such systems can completely change the dynamics of the system even destroying the chaotic behavior. Fourth order Runge – Kutta algorithm is used here to design the chaotic oscillator. In this paper the clock division, floating point adder and field function generation is implemented in Verilog. Stability analysis of the system suggests the range of step size values. IEEE 754 standard floating point arithmetic is implemented with some normalization steps.

The simulation is done by using Xilinx 14.5 software tool. The clock decision is mainly depends on the algorithm used in this design.

Keywords– Chaos theory, Runge-Kutta, Verilog, Xilinx

INTRODUCTION

The chaotic systems are deterministic because they are governed by some mathematical model. The chaotic oscillators mainly depend on initial conditions and step size.Initial conditions effect is popularly referred as the Butterfly effect .The step size parameter h will be used in design algorithm in further part of the project. The design process is subdivided into 3 parts.

Clock division and floating point adder

Field function generation

Slope generation

First part is done with simulation outputs. The clock is initially divided into 34 clock cycles. Fourth order algorithm suggests getting 136 clock cycles. The 16-bit floating point arithmetic is implemented which first normalizes the number to perform addition. Some precision will be lost because of normalization process. Runge-Kutta formulas are among the oldest and best understood schemes in numerical analysis. However, despite the evolution of a vast and comprehensive body of knowledge, it continues to be a source of active research. Runge-Kutta methods provide a popular way to

solve the initial value problem for a system of ordinary differential equations.The construction of higher order ones is very complicated and many extra stages have to be inserted for achieving accuracy of the same magnitude with the basic formula.Such accuracy is useful in astronomical applications like LISA program which is space mission to be launched.

RUNGEKUTTA METHOD

Eulers method and the improved Eulers method are the simplest examples of a whole family of numerical methods to approximate the solutions of differential equations called Runge-Kutta methods.

The trickiest part of using Runge-Kutta methods to approximate the solution of a differential equation is choosing the right step-size. Too large a step-size and the error is too large and the approximation is inaccurate. Too small a step- size and the process will take too long and possibly have too much round of error to be accurate. Furthermore, the appropriate step-size may change during the course of a single problem. Many problems in celestial mechanics, chemical reaction kinematics, and other areas have long periods of time where nothing much is happening (and for which large step- sizes are appropriate) mixed in with periods of intense activity where a small step-size is vital. What we need is an algorithm which includes a method for choosing the appropriate step- size at each step.

The Runge-Kutta-Fehlberg methods do just this. There are many different Runge-Kutta-Fehlberg methods, all of which involve comparing two different Runge-Kutta approximations to get an estimated error and step-size. The RK2(3) method is a low order method which gives moderately accurate results with only 3 function evaluations at each step. If high accuracy is important, you should use a higher order method. On the other hand, if you just need an answer to within 1% for a problem that doesnt cover too large a range of x values, the RK2(3) method is quick, cheap and effective (with the recommended tolerance of T = .001).

The RK4 discrete system for the continuous system given by Eq. 1 is, [5]:

x(n 1) x(n)

1 k1 (n) 2k2 (n) 2k3 (n) k4 (n)

6 x x x x

y(n 1) y(n)

1 k1 (n) 2k2 (n) 2k3 (n) k4 (n)

6 y y y y

Fig.1 Stability graph of fourth order Runge-Kutta algorithm

z(n 1) z(n)

1 k1 (n) 2 k2 (n) 2 k3 (n) k4 (n)

(1)

IV. ARCHITECTURE

6 z z z z

.

Wherex(n),y(n), and z(n) are the time series that constitutes the output of the project, and the values of for i = 1, …, 4

The process starts when the initial conditions for the state variables {x0, y0, z0} are loaded in the Register. Values are simultaneously sent to the rst and second adder. The block

k- generator is loaded with a zero value.

are:

x

k1 (n) h f

x(n), y(n), z(n)

x

The block Field function produces the value to which are available at the input of the block Slope generator.

The block Field function requires at least 34 clock cycles of

1 1 (n)

1 (n)

the main clock (clk) to nish all the calculations and give a

k2 (n) h f x(n) kx , y(n) k y , z(n) kz

valid result for f. That is the reason c0 = clk/34. Furthermore

x x 2 2

2

four cycles of c0 are required to get the new value of the time

2 k2 (n)

2 (n)

series. Consequently the overall frequency turns out to be c1 =

k3 (n) h f x(n) kx , y(n) y , z(n) kz

c0/4 = clk/136.

x x 2 2 2

Slope generator

F P

+

k4 (n) h f x(n) k3 (n), y(n) k3 (n), z(n) k3 (n)

x x x y z

F(), Field function

O/p

Where h is the step size. Similar expressions are obtained for y and z.

STABILITY OF RUNGE-KUTTA METHOD

generator

FP +

It is known that RK methods with xed step size h are stable if hi D for all Eigen values i of the local linearization, where D is a domain that can be calculated from the particular method employed. Specically, for the classical fourth-order method (RK4) applied to a system with real Eigen values; the stability requirement is essentially that hi (2.79, 0). Therefore, the largest magnitude eigenvalue limits the size of the largest stable step size. Our linearized system has eigenvalues of 1 = 2 cos (), 2 = 0. Assuming we are near

I/p

Clk

K generator

1/34

1/(34*4)

Reg

Fig.2 fourth order Runge-Kutta oscillator architecture

the steady state solution, sin () .25 yields 1 1.93. Therefore, we expect h < 1.44 for stability. The stability polynomial is

= 1 + ( )_1 (2)

And it is required thatR(h)<1 for absolute stability. The stability region is plotted using Map as follows

This block produces the output sent to the second Adder to obtain the new value of x1. Identical blocks are used for variables y and z. Once x1, y1and z1 are known they are sent to the block Register andthe cycle starts again. Blocks k- generator and Field-function constitute the brain of the RK4 solver and are reused as explained above to reduce the required FPGA area and power.

RESULTS

It is well known that chaotic systems are very sensitive to initial conitions. Consequently it is not possible to compare different realizations of the same system by means of the respective time series. It was shown that a statistical evaluation of the respective time series is a better methodology [7, 6, 4].The systematic statisticalevaluationofdifferentrealizationsinFPGAisawork in progress, but preliminary results show that the implementation in RK4 presented here may be used to produce chaotic time series with the same statistical properties than those obtained by numerical integration with more involved variable step methods, up to h = 0.05.

Thisvalueofhrepresentsanimportantimprovement over our previous realization using the Euler algorithm that required h

0.0045 [5]. These 10 times higher h implies that the number of time intervals required to cover a given evolution time is reduced in a factor 10 and then it reduces the FPGA memory bits required.

.

CONCLUSION

A method to real time implementation of a dynamical chaotic system onto a FPGA board is introduced. In free resources it is possible an improvement of the proposed design. Future work will include the use of pipelining, parallel computation and variable step algorithm.

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