- Open Access
- Authors : Neha Deshpande, Sowmya K B
- Paper ID : IJERTCONV8IS17004
- Volume & Issue : ICEECT – 2020 (Volume 8 – Issue 17)
- Published (First Online): 08-12-2020
- ISSN (Online) : 2278-0181
- Publisher Name : IJERT
- License: This work is licensed under a Creative Commons Attribution 4.0 International License
A Review on ASIC Synthesis Flow Employing Two Industry Standard Tools
Department of Electronics and Communication
R.V. College of Engineering
Bengaluru, Karnataka, India – 560059
Sowmya K B
Department of Electronics and Communication
R.V. College of Engineering
Bengaluru, Karnataka, India – 560059
Abstract – The advancement in technologies and electronic design automation tools has made it possible to design ASIC chips and analyze its parameters
extensively. Design Compiler by Synopsys and Genus Synthesis Solution by Cadence are some of the EDA tools which are used for running synthesis flow for various blocks of hardware SoC design. This paper provides an insight to brief survey of the various techniques involved in synthesis flow using Design Compiler tool and Genus
Synthesis Solution tool. The techniques used in running the synthesis flow are designed such that parameters –
power, area and timing are optimized and results in enhancing the overall performance. Therefore, the brief
literature survey provides a comparison among the various proposed work in terms of optimized values of power, area and performance (timing)and the results
provide an overview of theparameters evaluation using both the tools.
Keywords – Application Specific Integrated Circuit, Register Transfer Logic, Electronic Design Automation, Design Compiler, Synopsys, Genus, Cadence, Synthesis, Optimization, Power, Area.
With the advent of technologies, it has become possible to design hardware for any block/module with the aid of ASIC design flow. Application Specific
Integrated Circuit is a chip designed mainly for a specific application like for a protocol, satellite, voice recorder etc. ASIC design flow includes a series of steps -chip design specification, architectural design, behavioral and functional modelling,logical implementation, synthesis and testing, floor planning and design layout. In order to meet the user requirements regarding design of chip, changes are done accordingly in design tools, procedures and software/hardware abilities. All the stages of ASIC design flow make use of electronic design automation tools that enables to implement the design and the necessary changes in the design through an efficient manner. Logical Synthesis is one of the stages of ASIC flow. Synthesis is defined as a process that involves three steps – translation, mapping and optimization. With the help of these three steps, synthesis converts RTL code (Verilog or VHDL) into gate level netlist. The conversion from RTL code into design with logic gates is done with the help of synthesis tools. The synthesis tools available are Design Compiler by Synopsys and Genus Synthesis Solution by Cadence. The main aim of employing these tools is to enhance the productivity during conversion of RTL code and to provide highest quality of reports at the end of implementation. Power, performance and area are three important parameters to be taken into consideration at every stage of ASIC flow. These parameters play a key role in defining the way tools can be used to obtain the best results. Obtaining optimal PPA along with trade-offs has led to improving the functionality of EDA tools. Therefore, EDA tools – Design Compiler and Genus Synthesis Solution play a crucial role in optimizing power, performance and area during synthesis process. II. SYNTHESIS FLOW
ASIC design flow is used for designing and implementation of architectural designs with the help of RTL code. Fig.1 shows the various steps involved in ASIC flow, thus the implementation of any design starts by providing its specifications and is completed with netlist handoff. Among all the steps, logic
synthesis is a methodology which transforms RTL (HDL or VHDL) code into anetlistdescribing the hardware (logic gates and the wires connecting them). Standard cell library consisting of basic logic gates
like AND, OR, and NOR, or macro cells like adder, multiplexers, memory, and flip-flops are used in logic synthesis. Standard cells libraries put together are called technology library which are used for optimizing the design. Main objectives of Synthesis are – to minimize area, to minimize power and maximize performance. Synopsys’s Design Compiler tool performs synthesis of a design by carrying out the following steps -analysing & elaborating the RTL code, applying design constraints to the design, compiling and optimizing the design followed by inspection of results (output files).
Fig. 2 and Fig. 3 show the steps involved in performing synthesis using Synopsys Design Compiler tool and Genus Synthesis Solution tool respectively. Firstly, libraries and designs are loaded, design constraints are applied, and the design is synthesized. The generated output files are analyzed and mainly parameters like power, area, timing paths and quality of reports are extracted.
Fig.1. ASIC Design Flow Fig.2. Steps involved in synthesis flow using Design Compiler tool by Synopsys Fig.3. Steps involved in synthesis flow using Genus Synthesis Solution tool by Cadence III. LITERATURE SURVEY
The different types of methodologies carried out in synthesis flow with the help of Design Compiler tool by Synopsys and Genus Synthesis Solution tool by Cadence is available in the literature. The main aim of all the proposed work is to improve the efficiency of synthesis flow and to reduce the three important parameters – power, timing and area significantly.
A comparative study of area, power and timing results of the case study which performs scan insertion synthesis and synthesis with and without constraints is
presented. With suitable inbuilt optimization and mapping techniques, Design Compiler performs synthesis and optimization and Conformal EC tool
performs Logic Equivalence Check (LEC) on the case study .
A technique for enhancing area, power and performance by applying an ungrouping method in synthesis stage of Design Compiler tool and an optimization method in floorplan, placement and clock tree synthesis of IC Compiler tool is proposed. The comparative analysis of results of concurrent clock and data optimization and conventional clock tree synthesis implies that with concurrent clock and data optimization technique area, power (static and dynamic), worst negative slack and total negative slack is improved. Therefore, the Synopsys tools work efficiently in improving the overall behavior of the
In paper  Genus Synthesis tool by Cadence in synthesis process, Synopsys IC Compiler tool in placement and routing and Tempus tool in sign-off static timing analysis is employed. VSDFLOW is tested on designs like picorv32 – a RISC-V CPU core
which makes use of 180nm PDK’s and 45nm PDK’s from OSU and Nangate respectively and comparison drawn based on the results of different combination of tools by running VSDFLOW multiple times shows
that with each design, the area is optimized.
A synthesis technique using Synopsys Design Compiler involving a combination of PTL and CMOS logic cells, which can be inserted into standard cell-
based design flow is proposed . The experiments based on UMC 90-nm technology conveyed that PTL surpasses CMOS in terms of parameters like power consumption, area, and area–delay–power product while hybrid CMOS/PTL yields better results in area-
optimization and delay optimization-based synthesis flow. Therefore, PTL and hybrid CMOS/PTL can be
employed in applications having delay, power and area as critical parameters in the design .
A VHDL code-based synthesis flow for FPGA design employing Xilinx PlanAhead tool is proposed.
With this tool, it is easier to perform synthesis of RTL code and helps in obtaining better results. High performance, good flexibility and code processing speed and the dynamic resources placement of modules are few advantages offered by PlanAhead tools which makes them convenient to be used for carrying out synthesis flow for any application .
Paper  focuses on power reduction in scan synthesis stage of automatic test pattern generator. The aim of reducing cell internal power, net switching power and total dynamic power by 50% is achieved by applying low power techniques to phase locked loop circuit with the aid of Synopsys Design Compiler tool.
Another important inference that can be drawn is that scan clock frequency reduction has impact only on power and not on IC’s functionality and performance. Thus, Synopsys DC tool plays a crucial in design for testability stage.
In paper  two techniques towards efficient VLSI circuitsare presented. Firstly, a group of graph-
based algorithms were proposed to come up with good QoR with the use of simple cells like inverters and either 2-input NAND/NOR or 2-input XOR/XNOR. The results showed that parameters like power, delay and transistor count was optimized. Secondly, a pattern-based algorithm was proposedto design xor-
and-inverter graphs using C+11 coding language. The proposed approaches resulted in 8-10% reduction in area, 5-13% reduction in power and 16-19% reduction in performance in comparison to reference tools.
A null convention logic based on Quasi-delay-
insensitive designsis proposed. The gates required to implement NCL design are 35% -43% less as
compared to conventional design. By changing the gate behaviour, null convention logic can be varied to generate NCL+, INCL, INCL+ and INV. The results of all the logics are compared in terms of total gates, total area, total leakage power and total dynamic power. Along with optimization techniques being included in these logics, it becomes possible to improve the parameters such as area and power (static
and dynamic) .
A synthesis methodology keeping in consideration the outcomes obtained post place and route and static timing analysisis presented. Physical synthesis is introduced in the flow where in adequate physical information is available in earlier stages which allows to improve timing, power post signoff process and provides less violations in the initial iteration. Thus, physical synthesis is an approach to mitigate the errors, provide optimal timings results pre and post
placement and routing and help in reducing total
runtime from synthesis to signoff as violations were
reduced in the beginning iterations .
Paper putsforward the method of Boolean matrix factorization involving approximate logic. The main of the proposed technique is to break down large circuits to smaller blocks which makes it easier to perform Boolean matrix factorization on them. The results conveyed that with significant trade-off, it is possible to accommodate all the QoR metrics in factorization. Therefore, with the introduction of this technique, new ways to improve the efficiency of synthesis has been obtained.
Vedic mathematics in the design of 24-bit floating point multiplierhas been introduced in this proposed work. The multiplier design is simulated using Xilinx ISE 12.1 software and synthesized using CADENCE Genus synthesis solution tool. Comparison is drawn between critical parameters -area, power and timing using Xilinxsoftware and Cadence tool and it was observed that better results were gained with the aid of Cadence tool. So, these multipliers are better compared to conventional ones as the main benefit is less area and power consumption and enhanced performance .
A functional-flow parallel programming language Pythagoras based VLSI synthesis procedureis proposed. This supports in conversion of architectural description into RTL code and enables to execute verification, testing debugging and optimization with theaim of achieving reliability and quality with reduced timing. As a result, this concept is recommended for carrying out synthesis on system components for control systems and spacecrafts .
A HEVC based 8 point 2-D Discrete Cosine Transform stage whichis fabricated of adders that are efficient in terms of power and energyis designed in this proposed work. The architecture was designed using Verilog HDL and synthesized using Cadence Genus Synthesis Solution tool. Two important observations derived from the synthesized results of proposed design were reduction of 14.76% and 13.99% in power consumption and area respectively when compared to design made up of standard adders. Therefore, these results imply that discrete cosine
transform designed with proposed method can be used effectively in image and signal processing applications
In paper , synthesized designed elliptic curve
point multiplication method using FPGA and ASIC technologyis presented. Comparative study is carried out bysynthesizing the VHDL code on Virtex 6, Virtex 7 and using 65 nm United Microelectronics
standard cell library of Synopsys DC tool. It was observed that delay is less in ASIC technology than that obtained using Virtex 6 and Virtex 7. Hence, ASIC based flow is a more appropriate method for implementation than FPGA as parameters can be easily optimized to the required optimal values.
A low power design flow based on UPF as UPF is a format which provides all the details regarding different low power techniques being implemented in the flowis proposed. The proposed flow implements clock gating, multi voltage, power gating methods using Synopsys tool involving two libraries – 90nm and 32/28nm on a multiplier design. Thus, UPF plays an important role in the synthesis flow as it determines power which is vital parameter for any design .
In all the real time applications, synthesis flow plays a vital step in providing various details about a block/module such as – clocking paths being used, timing related information like hold time, setup time, worst negative slack, total negative slack, static and dynamic power consumption with respect to combinational and sequential instances in the design, information regarding number of ports, nets,
cells(combinational and sequential), macros present in the design and area occupied by each of them and most
importantly it generates the optimized RTL netlist
which is used in chip fabrication.
The outline of the steps carried out in synthesis flow is as shown in Fig.4. It starts with collecting all the necessary input files – verilog file consisting of RTL code, library list(technology library, symbol library, DesignWare library), constraints file and script file for the tool(.tcl file). The further steps involved are compiling library files to generate db files(binary format), performing analyze to read RTL code and to check for syntax errors. Elaborate step is mapping the RTL code to GTECH (technology independent) library cells. In compile and optimization step, optimization is performed at architectural, logic-level and gate level. Gate level optimization marks the end of the synthesis flow. Lastly, output files like log files, check files, reports (area, power, port, quality of report) and optimized netlist (.v format) is generated.
Fig.4. Detailed description of the steps followed in synthesis flow
In the proposed work, focus is on performing synthesis flowon a block which can bemodelled as
hardware accelerator using Design Compiler tool and Genus tooland to compare the Quality of Results as
shown in Fig. 5 and Fig.6 which are templates of QoR obtained using Design Compiler and Genus respectively. In general, on the basis of comparative analysis of Quality of Resultsof both the tools, it is
observedthat Design Compilertool is efficient in terms of area and power consumption.So,if Design Compiler tool can achieve good timing performance then it is preferred over Genus as it yields better results for area and power parameters when compared to Genus. Fig.5. Quality of Result Report for Design Compiler Tool Fig. 6. Quality of Result Report for Design Compiler Tool
The outcome of the proposed work has diverse
applications in the field of VLSI and SoC design and the main objective is to inculcate various techniques
in the synthesis flow methodology so that there is a wide scope of improvement in the results obtained which in turn plays a crucial role while performing activities such as design for testability, static timing analysis, formal verification etc. From the literature survey it is evident that in all the proposed work, the stages of synthesis flow are modified in such a way that designed techniques are being utilized to the maximum extent to produce efficient results.
Therefore, from Quality of Results of the both the tools it is conveyed that the flow aimsat PPA exploration, which means minimizing power, maximizing performance and minimizing area which are of upmost
importance in synthesis flow and ASIC design.
S. Gayathri and T. C. Taranath, “RTL synthesis of case study using design compiler,” 2017 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), Mysuru, 2017, pp. 1-
S. Iyengar and L. Shrinivasan, “Power, Performance and Area Optimization of I/O Design,” 2018 International Conference on Inventive Research in Computing Applications (ICIRCA),
Coimbatore, 2018, pp. 415-420. K. P. Ghosh and A. K. Ghosh, “Technology mediated tutorial on RISC-V CPU core implementation and sign-off using revolutionary EDA management system (EMS) —
VSDFLOW,” 2018 China Semiconductor Technology International Conference (CSTIC), Shanghai, 2018, pp. 1-3.
S. Hsiao, M. Tsai and C. Wen, “Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 1, pp. 21-
25, Jan. 2010.
M. A. L. Sarker and M. H. Lee, “Synthesis of VHDL code for FPGA design flow using Xilinx PlanAhead tool,” International Conference on Education and e-Learning Innovations, Sousse, 2012, pp. 1-5.
 A. Yadlapati and H.K. Kakarla, “Low-power design-for-test implementation on phase-locked loop design,” Measurement and Control, June 2019.
J. M. Matos, J. Carrabina and A. Reis, “Efficiently Mapping VLSI Circuits With Simple Cells,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
vol. 38, no. 4, pp. 692-704, April 2019.
M. T. Moreira, P. A. Beerel, M. L. L. Sartori and N. L. V. Calazans, “NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 6, pp. 1981-1993, June 2018.  L.E.Geralla, M.J.D. Guzman, and J.A. Hora, “Optimization of Physically Aware Synthesis for Digital Implementation Flow,” International Journal of Engineering and Technology, pp. 31-35, April 2018.
S. Hashemi, H. Tann and S. Reda, “BLASYS: Approximate Logic Synthesis Using Boolean Matrix Factorization,” 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), San Francisco, CA, 2018, pp. 1-6.  S. Javeed and S.S. Patil, “Low Power High Speed 24 Bit Floating Point Vedic Multiplier using Cadence,” International
Research Journal of Engineering and Technology (IRJET), vol. 05, no. 07, July 2018.
O.V. Nepomnyashchiy, I.V. Ryjenko, V.V. Shaydurov, N.Y. Sirotinina, A.I. Postnikov, “The VLSI High-Level Synthesis for Building Onboard Spacecraft Control Systems,” in Proceedings of the Scientific-Practical Conference “Research and Development – 2016”.
L. F. Sequeira et al., “Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors,” 2018 16th IEEE International New Circuits and Systems Conference (NEWCAS), Montreal, QC, 2018, pp. 309-312.
 M.S. Hossain, E. Saeedi and Y. Kong, “Parallel pointmultiplication architecture using combined group operations for high-speed cryptographic applications” PLoS ONE 12(5), May 2017.
V. Gourisetty et al., “Low power design flow based on Unified Power Format and Synopsys tool chain,” 2013 3rd Interdisciplinary Engineering Design Education Conference,
Santa Clara, CA, 2013, pp. 28-31.
Synopsys.(2011)., Design compiler user guide.
Cadence.(2019)., Genus user guide.