A Novel Fifteen Level Asymmetric MLI with Reduced Switching Devices and THD

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A Novel Fifteen Level Asymmetric MLI with Reduced Switching Devices and THD

Dr Ramesh H R, Professor Bandhavya C S, P.G.Student

Department of Electrical Engineering Department of Electrical Engineering University Visvesvaraya College of Engineering University Visvesvaraya College of Engineering

Bengaluru, India Bengaluru, India

Abstract – This paper presents a novel fifteen level asymmetric MLI with lesser number of components. This inverter topology is asymmetric in nature and contains three unequal DC voltage sources. It consists of reduced semiconductor devices which reduce circuit complexity, installation area and cost of the system. The proposed topology also decreases Total Harmonic Distortion (THD) which leads to better efficiency and voltage stress on the devices will be decreased. The analysis is done with Half-height Pulse Width Modulation technique. The inverter is simulated in Matlab/Simulink Software.

Keywords – Asymmetric MLI; Pulse Width Modulation; Efficiency; Total Harmonic Distortion(THD).

  1. INTRODUCTION

    Multilevel inverters (MLI) are the most important tool of power converters used elaborately in high and medium power applications [1]. Compared to two level and three level inverters, multilevel inverters gives the output voltage nearer to sinusoidal waveform. For this reason, the researchers have been proposing MLI topologies of higher levels. If frequency of switches is low, switching devices of multilevel inverters gives better performance and switching losses will be reduced [2-5].

    Three classical topologies of multilevel inverters are Diode- clamped or Neutral- point- clamped (NPC) [6], Flying- capacitor (FC) [7] and Cascaded H-Bridge (CHB) [11]. But diode- clamped and flying- capacitor inverters suffer from dc- link voltage balancing problem, bulk size of capacitor and more number of semiconductor components in more levels.

    The cascaded multilevel inverters provide an important solution to overcome limitations in operating voltage of the inverters. In this way, these kind of multilevel inverters current of switching devices is same as the output current. CHB multilevel inverter consists of many H-bridges which are connected in series, if the number of voltage levels increases number of semiconductor components also increases [8-10]. To overcome these problems, a novel 15-level MLI is presented on the basis of series connection of DC voltage sources. It consists of minimum number of IGBT switches and DC voltage sources. THD is also reduced. For 15-level output waveform proposed topology gives lower THD compared to other topologies [11-15].

  2. PROPOSED MULTILEVEL INVERTER The configuration for proposed MLI topology is shown in

Fig. 1. It involves ten IGBT switches and three dc voltage

sources to produce 15-levels in the output. This inverter topology uses three dc voltage sources 1, 2 and 3 of values

, 2 and 4 . The switches 11, 12, 13, 21, 22 and

23 turns ON and OFF to generate 15 levels in the output of inverter. This section is known as level generation. It is possible to connect n number of IGBT switches in level generation section to produce n levels in the output voltage.

In order to change the polarity of the output waveform, a set of switches 1, 4 form H-bridge operates for positive half cycle and other set of switches 2, 3 operates for a negative half cycle. This section is called polarity generation. In this topology, maximum switches conducting at a time are four. Hence voltage stress on the semiconductor devices will be low.

Fig. 1. Proposed MLI topology

The operating principle for the proposed multilevel inverter is illustrated in Fig. 2. Current paths in the positive half cycle are represented by dark lines. The zero state in the circuit is obtained by turning ON the upper switches (1 3) or lower switches (2 4) of the H-bridge.

(Mode 1- 0V)

(Mode 2- )

(Mode 3- 2 )

(Mode 4- 3 )

(Mode 5- 4 )

(Mode 6- 5 )

(Mode 7- 6 )

(Mode 8- 7 )

Fig. 2. Different modes of operation for output levels and current paths in the positive half cycle

During the positive half cycle, switches 1 and 4 are always ON, and switches 2 and 3 are OFF. Therefore, output voltage is positive. During the negative half cycle, switches 2 and 3 are always ON, and switches 1 and 4 are OFF. Hence, the output voltage is negative. Here, switches 1, 2, 3

and 4 determine whether the output voltage is positive or negative. The details about the switching states and voltage levels of output for the proposed MLI topology are presented in Table I.

From 270 degree to 360 degree, switching angles are calculated by the equation

31 = 2 – 1, 2 – 2 ., 2 – 1

2 2 2

TABLE I

SWITCHING STATES AND CORRESPONDING OUTPUT VOLTAGE LEVELS

For a 15-level inverter, the switching angles calculated for Half-Height PWM are: 1 = 4.096, 2 = 12.37,3 = 20.92,4 = 30, 5 = 40, 6 = 51.78° and 7 = 68.21°.

Voltag e levels

Switching states ( ON=1, OFF=0)

7

0

1

0

0

1

0

1

0

0

1

6

0

1

0

1

0

0

1

0

0

1

5

1

0

0

0

1

0

1

0

0

1

4

1

0

0

1

0

0

1

0

0

1

3

0

0

1

0

1

0

1

0

0

1

2

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

1

1

0

0

1

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

1

0

1

1

0

2

0

0

1

1

0

0

0

1

1

0

3

0

0

1

0/p>

1

0

0

1

1

0

4

1

0

0

1

0

0

0

1

1

0

5

1

0

0

0

1

0

0

1

1

0

6

0

1

0

1

0

0

0

1

1

0

7

0

1

0

0

1

0

0

1

1

0

Voltag e levels

Switching states ( ON=1, OFF=0)

7

0

1

0

0

1

0

1

0

0

1

6

0

1

0

1

0

0

1

0

0

1

5

1

0

0

0

1

0

1

0

0

1

4

1

0

0

1

0

0

1

0

0

1

3

0

0

1

0

1

0

1

0

0

1

2

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

1

1

0

0

1

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

1

0

1

1

0

2

0

0

1

1

0

0

0

1

1

0

3

0

0

1

0

1

0

0

1

1

0

4

1

0

0

1

0

0

0

1

1

0

5

1

0

0

0

1

0

0

1

1

0

6

0

1

0

1

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0

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1

1

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7

0

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0

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0

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1

0

The switching angles for second (90 to 180 degree), third (180 to 270 degree) and fourth (270 to 360 degree) quadrant can be calculated by using above equations.

IV. SIMULATION RESULTS

The analysis for proposed fifteen level asymmetric MLI is performed by Matlab/Simulink Software. The proposed inverter has 3 dc voltage sources and the set values are 1 =

10, 2

= 20 and 3

= 40. The fundamental output

III. PWM TECHNIQUE Semiconductor devices in the MLI must be operated in

such a way that appropriate output voltage levels are produced with reduced THD. Pulse width modulation techniques which are used in MLI are categorized based on frequency of switches. In this paper, Half-Height PWM method is used.

The Half-height (HH) PWM method can be explained as, when the fundamental value increases to the half-height of the level, the switching angle is set. In this method, the main switching angles are obtained by using the equation

voltage frequency is 50Hz. The load resistance of 100 and inductance of 1mH is taken.

In this paper, Half-Height pulse width modulation technique is used to control the proposed multilevel inverter. Fig.3. shows the simulation model for proposed 15-level MLI. Fig. 4, represents 15 levels in the output of proposed inverter topology and Fig. 5, represents the FFT analysis of the output waveform by using Half-Height Pulse Width Modulation (PWM) method.

(2 1)

= sin1

( 1)

Where i=1, 2, 3, 41

2

and m= number of output

voltage level. Switching angles calculated from 0 degree to 90 degree refers to main switching angles. Switching angles for second, third and fourth quadrants can be calculated as follows.

From 90 degree to 180 degree of the output waveform, the switching angles can be calculated by using the equation

+1 = – 1, – 2 , – 1

Fig. 3. Simulation Model for proposed 15-level MLI

2 2 2

From 180 degree to 270 degree, switching angles are calculated as

= + 1, + 1

2

Fig. 4. Output waveform for proposed MLI

Fig. 5. Harmonic analysis of output waveform

Comparison of THD for different topologies

Table II: Comparative study for different 15-level MLI topologies.

Topologies

No. of levels

No. of switches

No. of DC sources

THD%

[12]

15

12

3

12.36

[13]

15

10

3

10.56

[14]

15

10

3

8.98

[15]

15

10

3

8.77

[16]

15

12

3

7.85

Proposed

15

10

3

5.48

From Table II, it can be concluded that the proposed topology showing better performance with respect to switching devices and Total Harmonic Distortion (THD) compared to other given topologies. In MLI topologies, as number of levels increases THD will reduces and reduced THD gives better efficiency and power quality.

V. CONCLUSION

This paper presents a novel fifteen level asymmetric MLI. This proposed topology containing 10 IGBT switches and 3 dc voltage sources to produce 15 levels in the output of the inverter. It was shown that the proposed inverter uses reduced numbr of semiconductor elements as compared with other topologies, it also gives reduced THD and better efficiency. THD of the inverter is 5.48%, obtained by fundamental Pulse Width Method (PWM) like Half-Height method.

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