 Open Access
 Authors : Raed Althomali
 Paper ID : IJERTV9IS090492
 Volume & Issue : Volume 09, Issue 09 (September 2020)
 Published (First Online): 02102020
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
A Novel Exponential PulseDecay Modulation Multiplier for VLSI Neural
Raed Althomali
Department of Electrical and Electronics Engineering, Yanbu Industrial College,Yanbu AlSinaiyah, KSA
Abstract: This paper introduces a new EPDM multiplier circuit
t
based on the dynamic charge of MOSdifferential configuration resistor. In addition, shows that the actual response of a
Q e
U(t) dt
(1)
conventional EPDM multiplier is not linear and pseudo linear resistor realization is VDS and VTN dependent. This active resistor has matched devices biased in the triode region and enables the multiplier to enhance the output linearity. The proposed technique removes the influences of bulksource and drainsource voltages on circuit resistance by taking into account the effects of channel length modulation, making the developed new multiplier suitable enough for the architectures implementation of several analog VLSI neural networks.
, where U t are the step function and Q is the charge delivered. and are constant values controlled by the
input and weight signals respectively. The neuron input signal with its weight simultaneously enables two quadrant multiplication complementary arrangements to charge packet of the distribution bus.
I K\ W V V
1 V 2
(2)
Index TermsArtificial Neural Network, Synapse circuit design and Exponential Pulse Decay Modulation Technique.

INTRODUCTION
The application of artificial neural networks (ANN) in analog chip designing resulted in the solutions to problems of geometry, propagation delay, parametric nonlinearities and power consumption which were once considered difficult. [2] And [7] have shown that, due to its power consumption and critical matching, designing of an analog multiplier is among the challenges of analog circuit design. The multiplier finds it applications in communication circuits, including filters,
TN N L n TN n TN 2 TN
From equation (2) it is evident that device N2 always conducts in the saturation region and succeeds to regulate the dependence of overall currents of N1 and N2 on the square of n . On the other hand, the coefficient '' that represents the linear dependence of ID on VDS increases considerably for the very short transistor VDS , and has considerable effect on ID in the saturation region, as shown in the following equations.
+VDD
modulators and mixers, and can be implemented using both BJT and MOS technologies [14], [15], and [16]. Since BJT consumes more power, the MOS multiplier with active load resistor becomes strong candidate for ANN usage for low
Clock
Vs
Dynamic
N4 Signal
V's
P4 Ccp
P1 P2 P3
NODE A
power design. Under the conditions of negligible channel length modulation and mobility reduction, [3], [6] and [11] have shown linear response of an EPDM multiplier when compared to conventional analog techniques in terms of low power and area requirements. An EPDM multiplier
Clock
N5
VSS
Vw
Ccn
NODE B
N1 N2
ExcOut
InhOut
Cbus N3
independent of VDS and VTH changes is proposed. The paper is divided into following sections: Section II and III present the basic operation and design of a conventional and modified EPDM multiplier with double MOS configuration,
Static Weight CW
VSS
respectively. Section IV presents the analysis and results of SPICE simulation of both types of EPDM multipliers. Section V elaborates on the comparison of both EPDM circuits
Figure 1: Circuit of the EPDM multiplier circuit.
followed by the conclusion.
I K\ W V V 2 1 V

With
D GS TH DS
2L


II. THE CONVENTIONAL EPDM CIRCUIT
The conventional EPDM circuit, as shown in Figure 1,
channel length modulation, the currents become:
d
modulates the input by a weight signal through the decay time of a singlesided exponential current pulse. The
ITN
CTN dt
(4)
delivered charge packet Q can be obtained using equation
1.
V2
ID4
M4 M3
ID3
VC2
V1
ID2
M2 M1
ID1
V2 V1
I2 I1
+VDD
VC2
VC1
VB
I2 V3
rac/2
I1 V3
rac/2
V3
VIN
Dynamic Signal
Ccp
Ccn
M9 M8
NODE A
NODE B
M7 M6
M10
M5
M11
11
Cbus
M12

(b)
Figure 2: (a) DoubleMOS differential configuration resistor

The equivalent circuit of the doubleMOS Differential resistor
Vw M4
Static Weight Cw
M3 M2 M1
VC1
VSS
, where CTN is the total capacitance at point B.
Figure 3: Schematic diagram of the new EPDM multiplier circuit.
V V 3 V t
C W DD TN


MODIFIED EPDM CIRCUIT
(t) V \ cn V V
2 n
n S C TN TN V V

2V e
TN
V
W DD
V 3 V
TN
I1 ID1

ID3
(8)
W
VTN
DD 2
TN
(5)
I 2 ID 2 ID 4
(9)
VW
VDD 2VTN
By using equations (8) and (9) to find (I1 – I2) gives:
W
1 W
I I I
K \ V
V V V
(10)
Q I
dt
K \ 2 (t) dt
(6)
TN 1
2 C1
C 2 1 2
n N 3 2 N L n
L
Clearly the amount of charge depleted over one clock cycle or
The equivalent resistor rac can be found as:
S
S
injected into the distribution bus is not linear and depends on the square ofV \ . This is because the pseudo linear resistor
formed by matched devices is not linear and depends on V 2
rac
V1 V2
I1 I2
1
C1 C2
C1 C2
K \ W V V
L
(11)
DS
and VTN as indicated in the equation (7).
1 ITN
K \ W [3 V 2

2V V
(7)
All devices are assumed to be in the ohmic region. Equation
R V
L 2 DS
DS TN
(11) only holds when:
DS
V , V min V V
, V V
(12)
V 2V
V 2 ]
1 2 C1 TH
C2 TH
GS TN 2 TN
Because of the nonlinearity in the distribution bus it is important to find an alternative circuit that not only makes the output linear, but also removes the influences of drain source voltage and bulk voltage, taking into consideration the channellength modulation.
To eliminate the influences of VDS, and VTN upon the AC resistor realization, a modification in the conventional EPDM circuit is made. The principle employed here is to use four identical devices biased so that the influences of VDS and VTN
By substituting the previous circuit of the AC resistor in the EPDM synapse multiplier circuit to become the modified EPDM multiplier circuit, as seen in Figure. 3.



ANALYSIS OF THE NEW EPDM MULTIPLIER
Referring to Figure 3 and the total current described by equation (10), it is interesting to compare the AC resistor realization between conventional and new EPDM circuits.
variations are canceled out. This design uses a doubleMOS
V V V
(13)
differential configuration resistor, as shown in figure. 2.
TN L W
C1 1 2
1 X
1 X
The characteristics of the AC resistance can be obtained by assuming all of the devices are matched and operate in the
V V
and
V2 VX

. where is a small value,
ohmic region. I1 and I2 are obtained as follows:
represent the voltage drop across the active resistor of
transistor M5 and VX
is the instantaneous voltage at node B.
ITN becomes as indicated below
I K \ W (V V )
(14)
channel MOS transistors having W/L = 5/2 and model
TN L W C1
parameters of VTH = .75V and KP = 8 A/VÂ².
Using equations (11) and (14) results in
K \ WV V
d L W C1
n
. (15)
d t CTN
rac CTN
Using Laplace transformation, it can be shown that:
S n
(s)
. (16)
S
(a)
The initial condition of n (t) is
(t 0) V
Cc n . (17)
n I N C
TN
Therefore,
Ccn
(18)
n (t)
t VIN C
TN
Q I
dt 1 K\ W (V
V ) dt
(19)
2
2
n M
12 L
GS12 TH
2
2
(b)
GS
GS
V
12
VTH
VX VDD VTH
n (t)
(20)
Figure 4: SPICE simulation results showing the signal outputs on nodes A & B with different weight voltage of: (a) 3V, (b) +3V.
Q 1 K \ W 2 dt
(21)
n 2 L n
The double MOSFET differential resistor is found to be superior in linearity and can be operated under VDS and VTH variations. In the operating region (ohmic), and to avoid more
complications in the system model, there is no physical
justification to multiply 1 VDS with the drain current.
Therefore, since
VDS is so small in that ohmic region and
(a)
has little effect on ID, a transient multiplier characteristic of an EPDM circuit and quadrant multiplier modified synapse circuit has been simulated in Figures 4 and 5. With Vinput of 5 V and Vweight of 0V, the transfer curves of this synaptic circuit for weights from 3 V to +3 V are shown. The DC bias voltages are 5V, 5V, 4V, and 3V for VDD, VSS, VC1, and VC2 respectively.
Both circuits are simulated by SPICE a simulator using N channel MOS transistors having W/L = 3/5 and model parameters of VTH = 0.75V and KN = 24 A/VÂ², and P
V. ADVANTAGE OF THE NEW EPDM MULTIPLIER
The modified EPDM circuit has added advantages when compared to the conventional circuit. Because there is no static path between bias voltages it will result in low power consumption when integrated at VLSI levels. It successfully reduced the influences of VDS and VBS by using the double MOS differential configuration with matched devices operating in the ohmic region, as indicated in Figure 6. The modified circuit not only makes the AC resistor linear, but removes the influence of the bulksource voltage. The effect of the channellength modulation has been reduced as all
(b)
Figure 5: SPICE simulation results showing the signal outputs on nodes A & B at M11 & M12, with different weight voltage of: (a)
3V, (b)+3V.
devices are operating at the ohmic region. And, since VDS is so small in this region, it has little effect on ID. Due to neglect of the channellength modulation and body effects, the output becomes more linear and the THD problem is ignored forever. The die area is small compared to the previous design because the smaller transistor dimensions can be chosen than those in the other circuit.
2
2
Although the linearity of the new circuit is very good over a wide range of input signals, the dependence of output charge
V
V
on S prevents this circuit from being an ideal linear multiplier. The combined transconductance (gm) of devices N1N4 (or P1P4) must be small enough to ensure a high
equivalent resistance between node B and VDD (or node A
V
V
S
S
and +VDD), to assure good capacitive coupling from \ to
node B (or to node A). It may happen to see an offset in the output due to nonideal matching between devices in the aspect ratios, parasitic capacitances, and threshold voltages.
IV. PROPOSED EPDM ANN SYNAPSE CIRCUIT
The suggested EPDM multiplier circuit shown at Figure 7 became the more suitable synapse circuit for building the new synapse memory matching cell.
N
N
N
N
The proposed circuit is basically an enhancement EPDM with two or more gates. One of the gates is left floating and other select gates act as the gate of a regular enhancement MOSFET. Referring to Figure 8 and the total current described by equation (22), that controls the ON and OFF states of biological neurons transistors by calculates the weighted sum of all input signals.
Figure 7: Equivalent of the proposed EPDM floating gate circuits
VFGS
FG
N
N

Ci
VG i VS
The operation of the new suggested synapse memory cell
shown in Figure 9 can be described by equation (23).
C0
Cj
i 1 C0

Cj
K V
*V C

K V
*V C
\ \
j 1
j 1
V
1 IN1 W 1 G1 2 IN 2 W 2 G 2
(23)
Where FG is the initial charge stored on the floating gate
out
CG1


CG 2
C0
due to the programming process.
I 1 C W (V V )2
DS 2 OX L FGS TH
With twoinputs, one acts as an input vector and the other as a template vector. Each is applied to the corresponding input of its multiplier. The weight signals of each chosen EPDM
multiplier are equal in magnitude and opposite in direction.
(22) 1 C
W (
Ci V
N
N
V V )2
The output of the two matched multipliers is out of phase.
N
N
2 OX L
N
G i
i 1 C0 Cj j 1
S TH
When V1~ = zero, the proposed inverter does not turn on because the floatinggate potential is a little smaller than its inverting threshold. The inverter gives an output of logic 1,
S TH
S TH
K ( Wi VG i i 1
V V )2
which is input to the CMOS inverter.
The CMOS inverter is then activated to give logic 0 outputs. The opposite action of this work is done. When V1~Vn are nonzero signals.
Figure 6: Equivalent of programmed floating gate circuits
Figure 8: The signal voltage at the floatinggate voltage at selected gates inputs (VG1 and VG2).
Figure 9: Simulation results of the suggested synapsememory cell at input signals VIN1=VIN2=10V and weight signals VW1=VW2=1V
The floatinggate potential of the proposed inverter is larger than its inverting threshold. It turns on and gives logic 0 output that turns off the CMOS inverter. The CMOS inverter gives an output of logic 1.
As shown at Figure 9, the results are accumulated on the MOS floating gate and the result is the difference between them.
The output illustrates either logic 1 or logic 0, according to the degree of matching between inputs.

ANALYSIS OF THE PROPOSED synapse memory cell
The proposed circuit has been utilized to produce the sum operation with no dccurrent flows. As a result, a dccurrent free operation of the cell has been established making it possible to build a low power system. The circuit is very simple in concept and constrution. It consumes a small chip area because there are no switches, as in most classical matching cells. The proposed synaptic memory cell design with floatinggate potential and realtime monitored during data writing achieves accuracy and high speed for analog voltage storage through the thresholding action of proposed inverter.
Because no complicated control circuitry is required for weight updating, the new version cell allows highdensity integration of a synapse cell as well as a highspeed learning operation of a proposed selflearning neural network. The static power dissipation in each inverter is zero in both of its states, where the dissipation due to the leakage currents is so small as to be neglible.
A lowresistance path exists between the output terminal and ground or VDD. These low resistance paths ensure the output voltage is independent of the exact values of W/L ratios or any other device parameters. Furthermore, the lowoutput resistance makes the inverter less sensitive to the effects of noise and other disturbances.
V. CONCLUSION
S
S
The proposed multiplier can modulate an input signal based on a locally stored weight voltage. The modified EPDM multiplier circuit can produce efficient computations in the analog domain with a reduction in power and area requirements. Although the linearity of the new circuit is very good over a wide range of input signals, the dependence of output charge on V2 prevents this circuit from being an ideal
linear multiplier. The average actual power consumption of the new circuit will be less when compared to a conventional EPDM circuit. The combined transconductance (gm) of devices N1N4 (or P1P4) must be small enough to ensure a
high equivalent resistance between node B and VDD (or node A and +VDD) to assure good capacitive coup ling from V\ to
S
S
node B (or to node A). There is a possibility of appearance of an offset in the output due to less than ideal matching between devices in the aspect ratios, parasitic capacitances, and threshold voltages.
Practically, I observe that the output of the proposed matching cell is not exactly zero. This is due to the nonperfect matched device parameters and the parasitic capacitance coupled to the floating gate.
The speed of operation of a digital system as a computer is determined by the propagation delay of the logic gates used to construct the system. To obtain lower propagation delay and faster operation, a higher process transconductance parameter should be utilized and the transistor W/L ratio increased. There are design tradeoffs because these conditions increase the dynamic power dissipation.
REFERENCES

R. Althomali, "A modified exponential pulsedecay modulation technique based on CMOS analog multiplier," 2017 International Conference on Communication and Signal Processing (ICCSP), CHENNAI, India, 2017, pp. 19671970. doi: 10.1109/ICCSP.2017.8286744

C. Bartolozzi and G. Indiveri, Synaptic Dynamics in Analog VLSI, Neural Computation, vol. 19, no. 10, pp. 25812603, 2007.

S. Moradi and G. Indiveri, An eventbased neural network architecture with an asynchronous programmable synaptic memory, TBioCAS, pp. 110, March 2013.

F. Galluppi, S. Davies, A. Rast, T. Sharp, L. A. Plana, and S. Furber, A hierachical configuration system for a massively parallel neural hardware platform, in Proceedings of the 9th conference on Computing Frontiers. ACM, 2012, pp. 183192.

J. Seo et al., A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons, in Proceedings IEEE CICC, 2011, pp. 14.

R. J. Vogelstein, U. Mallik, J. T. Vogelstein, and G. Cauwenberghs, Dynamically reconfigurable silicon array of spiking neurons with conductancebased synapses, IEEE TNN, vol. 18, no. 1, pp. 253 265, 2007.

F. Folowosele, R. EtienneCummings, and T. Hamilton, A CMOS switched capacitor implementation of the MihalasNiebur neuron, in BioCAS, 2009, pp. 105 108.

M. Noack, M. Krause, C. Mayr, J. Partzsch, and R. SchÂ¨uffny, VLSI implementation of a conductancebased multisynapse using switched capacitor circuits, in International Symposium on Circuits and Systems ISCAS 2014, 2014.

E. T. Rolls, L. DempereMarco, and G. Deco, Holding multiple items in short term memory: A neural mechanism, PloS one, vol. 8, no. 4, p. e61078, 2013.

C. Mayr and J. Partzsch, Rate and pulse based plasticity governed by local synaptic state variables, Frontiers in Synaptic Neuroscience, vol. 2, no. 33, p. 28, 2010.

O. Levy, N. Ziv, and S. Marom, Enhancement of neural representation capacity by modular architecture in networks of cortical neurons, European J. Neuros. , vol. 35, pp. 17531760, 2012.

M. Noack, C. Mayr, J. Partzsch, M. Schultz, and R. SchÂ¨uffny, A switchedcapacitor implementation of shortterm synaptic dynamics, in Proceedings MIXDES, 2012, pp. 214218.

M. Noack, J. Partzsch, C. Mayr, and R. SchÂ¨uffny, Biologyderived synaptic dynamics and optimized system architecture for neuromorphic hardware, in 17th International Conference on Mixed Design of Integrated Circuits and Systems MIXDES 2010, 2010, pp. 219224.

K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, and T. Sakurai, Managing subthreshold leakage in chargebased analog circuits with
lowvth transistors by analog T switch (ATswitch) and super cut off CMOS (SCCMOS), SolidState Circuits, IEEE Journal of, vol. 41, no. 4, pp. 859867, April 2006.

C. Mayr, M. Noack, J. Partzsch, and R. SchÂ¨uffny, Replicating experimental spike and rate based neural learning in CMOS, in IEEE International Symposium on Circuits and Systems ISCAS 2010, 2010, pp. 105108.

J. Hasler and B. Marr, Finding a roadmap to achieve large neuromorphic hardware systems, Frontiers in neuroscience , vol. 7, 2013.

S. Brink, S. Nease, P. Hasler, S. Ramakrishnan, R. Wunderlich, A. Basu, and B. Degnan, A learningenabled neuron array IC based upon transistor channel models of biological phenomena, Biomedical Circuits and Systems, IEEE Transactions on, vol. 7, no. 1, pp. 7181, 2013.

Dr. Raed Althomali was born in Saudi Arabia, in 1979. He received the B.S. and Electrical engineering from the Yanbu Industrial College, SA in 2008 and the
M.S. and Ph.D. degree in Electrical and Computer engineering in fiber optics and photonics from SIU, Illinois in 2014.
He currently is the Managing Director, Yanbu English Language & Prep Year Institute, Saudi Arabia. His main areas of research interest are signal processing, all optical devices, VLSI, active filters, and neural networks. Dr. Raed is a member of the Saudi Council of Engineers and Optical Society of America.