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 Total Downloads : 786
 Authors : Mala Mitra
 Paper ID : IJERTV1IS10557
 Volume & Issue : Volume 01, Issue 10 (December 2012)
 Published (First Online): 28122012
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
A LowCost Lightweight Random Number Generator Implementation
Mala Mitra
Department of Electronics and Communication Engineering, PESIT, Bangalore South Campus, Bangalore.
Abstract
In this paper, a true random number generator based on operational amplifiers is proposed. The circuit consists of an operational amplifier with a positive feedback. It is a Schmitt trigger without any applied input signal. The circuit gives a positive (bit 1) or negative (bit 0) saturated output voltage depending on the polarity of the differential input governed by the thermal noise voltage of the resistors. There is no need to amplify the noise voltage. The circuit response is analyzed with TINATI tool. The circuit is implemented using IC LM741 operational amplifier chip as well as on the onchip operational amplifiers of the MSP430 microcontroller. Due to low datarate, a small volume of data should be generated. These random data can be used as a seed value for a pseudo random number generator. The data passed NIST test. The generator can be implemented on WISP RFID tags, which have builtin MSP430 microcontrollers.
Keywords: NIST test, Operational amplifiers, Probability, Programmable circuits, Random number generation, Thermal noise.

Introduction
Random Number Generators (RNGs) are required in many fields of technology. It may be a MonteCarlo simulation or an optimization with Genetic Algorithm, or a digital circuit testing or a privacy and security algorithm. The robustness of the technology is primarily dependent on the quality of the Random Number Generator (RNG). Many RNGs have been proposed in recent times and in the past [1 – 24]. Depending on the operating principle, RNGs are classified into two categories: True Random Number Generators (TRNGs) and Pseudo Random Number Generators (PRNGs).
In a True Random Number Generator (TRNG) the input is extracted from a natural phenomenon which we believe to be random from our ageold
experience. Gaussian random thermal noise voltage in a resistor is a popular choice for a TRNG input. A very common strategy is to amplify this noise and to get random numbers from the polarity of the amplified noise with the help of a comparator. So far the output bit string showed nonrandom behavior as deterministic noise of the amplifier dominated over the input random thermal noise and the finite bandwidth of the amplifier colored the white noise [17].
Though a PRNG produces output bits by deterministic processes the complexity of the algorithm makes the bits to appear as random or unpredictable. Use of a mathematical series or use of sea of gates e.g. combination of shift registers and XOR gates is a standard practice. The generation starts from an initial state or seed value. A PRNG gives the same sequence of random numbers if the same seed value is used. Since the PRNG algorithm is available from the product and open to all the unpredictability of the bits lie with the secrecy of the seed value used. In an automated system like RFID user cannot input this secret or unpredictable value. If date or time is used as seed, unpredictability is lost. Apart from this problem, PRNGs are very efficient. Some of the recently proposed PRNGs [3, 4] pass the NIST test [25], the statistical test suite to certify that the data is unpredictable. Unlike TRNGs, PRNGs can deliver bits at a high datarate with nominal power consumption. For a lowcost solution, the algorithm can be implemented in the already existing microcontroller. As a contrast to PRNG, a TRNG delivers bits at a low datarate with high power consumption. All the reported TRNGs need analog circuits with complex controls. That makes it very difficult to fabricate and characterize the chip. In some cases, a part of the design is implemented on Si. In most of the cases, only simulated results are reported. In some cases, the product prototype is not lightweight. The main advantage of TRNG is: it does not require a seed value. A recent idea is to combine a TRNG and a PRNG [26]. A TRNG may be used to create a low volume of data needed for the seed value of the PRNG.
In this work, a TRNG is proposed that is suitable for generation of seed values. The TRNG is implemented on IC LM741 operational amplifier (opamp) chip and on the operational amplifiers (opamps) of the MSP430 microcontroller as well. The technology can be used in the popular WISP RFID tags with builtin MSP430 microcontrollers. MSP430 microcontroller is widely used for RFID tags as it can operate at ultralow power and it provides a great computational facility. C. Pendl et al. [27] showed that, ECC, a very computationally intensive asymmetric cryptographic algorithm for
Random thermal noise was amplified and applied to the Schmitt trigger circuit input. Two unanticipated problems occurred. Firstly, amplification introduced deterministic noise. Secondly, the trigger points were too closely spaced to change the output state [29]. It is to be noted that, in the proposed circuit, noise is not amplified its polarity at the instant of active supplies decides the output.
information security can be implemented on MSP430 microcontroller. Further, MSP430 has in built security sensors useful for RFID tags. RFID
R1 500
–
+
Output
ClockN
tags are prone to temperature and power attacks [28]. An adversary may make a temperature attack by deliberately changing the ambient temperature of the tag. Due to temperature variation, some of the bits may become predictable. MSP430 has an
R3 1k
!OPAMP
+
+ + Clock
inbuilt temperature sensor that may be used to interrupt bit generation when the temperature goes
Figure 1. Random Number Generator Circuit
out of range to prevent malfunction of the RNG. In case of a power attack, adversarys detector transmits less power to a passive RFID tag to predict the bits. The brownout detector of MSP430 can take care of this situation. Table 1 and 2 shows the interesting features of the recently proposed
R2 1k
RNGs. It can be observed from the Tables that for TRNGs either power consumption is very high or
For a single positive supply opamp a difference input Vdiff with a positive polarity is most likely to
datarate is low. Sometimes it does not pass the
NIST test. Implementation complexity is also there.
latch the output at V
sat
, the saturation voltage. If the
PRNGs work fine but seed value requirement may create a problem. In the next section the theory of random number generation for this TRNG is discussed.

Theory
The theory of random number generation in a dual supply opamp is much simpler as compared to that generated from a single supply opamp. In this paper, both the cases are discussed. Figure 1 gives the circuit configuration of an rng with a dual supply opamp. This is a Schmitt trigger circuit without any input signal. The positive and negative supplies are replaced by clock named as Clock and inverted clock named as ClockN. When Clock and ClockN are at 0 voltages the circuit output becomes 0 volt. At the instant when Clock becomes positive
and ClockN negative the output saturates to a positive or a negative value. The polarity of the
input is changed in subsequent instants, output remains Vsat as long as the opamp is on. For a negative polarity input at switch on, the output becomes zero and does not latch. At the next instant if the polarity is positive, the output latches. If the opamp remains on for a finite time the polarity must become positive at some instant and the ouput will be always Vsat. Let us assume that, the opamp remains on for slew time or the time taken by the output to change its state. The output will become Vsat if at the 0th instant or switch on instant Vdiff is positive. At the time of switch off the output will reach the highest level n corresponding to Vsat. A first time positive Vdiff at a later instant will reduce the output proportionately. In mathematical notations:
output is decided by the polarity of the difference input, resultant thermal noise voltages across the
Vdiff
Vth Voffs Vfb
(1)
resistors in this case. Since the polarity of the output is dependent only on the resultant polarity of the thermal noise voltages it is truly random.
The bistable states of a Schmitt trigger circuit was tried earlier to generate random numbers.
where Vth is the combined random thermal noise for the three resistors at any instant, Voffs is the offset voltage usually kept negative for a single
supply opamp to avoid thermal noise effects. Vfb is the feedback voltage and can be given as:
R3
of probability pgen and is given by: (1pgen) pgen. The probability approximates to pgen as pgen <<1. Similarly the probability that at instant 2 generation
takes place is the joint probability of: (i) no
R
Vfb
2

R3
Vout
(2)
generation at instant 0, (ii) no generation at instant 1, and (iii) generation at instant 2 and is given by:
(1pgen)2 pgen. The probability approximates to pgen
At the time of switch on or instant 0, the output voltage should be kept zero:
Vout (0) =Vfb (0) = 0 (3)
Vth can be negative or positive with equal probability of 0.5. The probability of positive Vdiff(0) is less than 0.5 as Voffs is negative. If Vdiff

is positive the voltage build up at the output starts. However, that build up may get destroyed at the next instant due to a dominating negative Vth. The next instant is defined when the Vth can change its polarity. The time between 2 consecutive instants tre depends on electron response time and tre
Â« T. where, T is the slew time, the time taken by the opamp to change its output state. Let the opamp is kept on for T. Let there be n+1 instants or n time slots then:
as pgen <<1. From this analysis, one can see that, generation instants are almost equally probable. The generated output voltages in the range 0 to Vsat forms a continuous pattern as tre <<T and are roughly equally probable. If these analog voltages are expressed in binary it is expected that the bits will be random. The next section gives the implementation and measurement details of these circuits.



Measurement results
The circuit given in Figure 1 was implemented on a breadboard with IC LM741 dualsupply op amp. Instead of using clock pairs the supply switch was made onoff. This eliminates the possibility of a clock skew and a residual charge buildup (discussed in Sec. 2) at the output. For the dual
supply opamp 289 data were collected. Some of
T ntre
(4)
the tests in NIST require 106 bits. Only those tests with recommended data size less than 289 were
Thus, there are (n+1) output states corresponding
to (n+1) generation instants. A positive Vdiff does not guarantee a build up. It may get destroyed in subsequent instants. Assuming the output voltage develops linearly with time the output voltage at instant 1 for a positive Vdiff (0):
carried out. The details of the tests were reported elsewhere [30]. All the tests were passed.
The proposed circuit was also implemented on the three opamps available in the MSP430FG4618 microcontroller. The circuit configuration requires two modifications from Fig. 1: (i) instead of dual
supply only a single positive supply is available (ii)
Vout

treVsat
T
(5)
instead of a clock pair programming language instructions were used to make it on/off. Unfortunately, there is no instruction available in
The output voltage build up can be destroyed for negative Vdiff for the condition obtained from Eq. 1:
MSP430 to connect the onchip resistors in the positive feedback mode. Opamp was configured in generalpurpose mode with the two inputs and the
0 [Vth (1) Voffs ] Vfb (1)
(6)
output connected at three port pins. External resistors were connected to these pins.
Let pgen be the probability that generation takes place. Clearly pgen<<0.5 due to (i) negative offset voltage and (ii) possibility of destruction of positive voltage build up. The probability that at instant 0 generation takes place is pgen. The probability that at instant 1 generation takes place is the joint probability of: (i) no generation at instant 0 of probability 1 pgen and (ii) generation at instant 1
In MSP430 three slew rates are available. The slowest slew rate, 0.3 V/ÂµS, was selected. This gives a slew time of 8.933 ÂµS for the saturation voltage same as supply voltage VCC =2.68 V. As discussed in sec. 2, it is expected that the opamp should produce equally probable output between 0 and 2.68 V, if it is switched on for the slew time. For a switch on of 8.9 ÂµS the observed output was close to zero for most of the time. The switch on
time was increased approximately to a value of 11
ÂµS where the binary equivalents of the outputs gave equal number of 0s and 1s. The increase in time might be due to a latency required by the opamp to get on after the instruction is executed in MSP430. This latency was also observed in simulation as discussed in Sec. 4. The time was adjusted only once, no further adjustment was necessary for long time use heating or ambient temperature variation.
For further applications, the analog output voltage can be converted to binary with the use of the onchip ADC. In this work, for data analysis the analog voltage was measured at a port pin with a voltmeter with 2 decimal point resolution, and typed to a datafile. The voltage should be scaled in the range 0 to 255 for 8 bit binary. To avoid the roundoff error, which is, slightly deterministic each analog voltage is multiplied by 100 and converted to 8 bit binary. For analog values greater than 2.55 the most significant bit was thrown. In this way 4 bits were ignored that is immaterial for a statistical test.
At every switch on the output voltage or the residual charge at the output should be zero. To ensure that, the opamp was switched off for 5.5 ÂµS followed by a negative feedback configuration for 11 ÂµS and then switch off for 5.5 ÂµS. For negative feedback same instruction as positive feedback was used except the + and inputs were interchanged. Table 3 gives the sequence. The sequence repeats after 6 timeslots.
In each time slot of 11 ÂµS one opamp in positive feedback configuration produces 8 bit
seed value is unpredictable. From the theory of generation, it seems the data is random and a large volume of data should pass the remaining tests as well.


Simulation results
To analyse the behaviour of random number generation for a dualsupply opamp simulation was done in TINATI tool. This is a tool developed and supported by Designsoft and Texas Instruments. IC LM741 opamp [32] was configured in TINATI. The circuit is given in Figure 1. In this simulator resistors cannot be modelled for thermal noise voltages. To understand the effect of thermal voltage Vdiff, input pulse of amplitude – Vdiff is applied at the inverting terminal of the opamp.
The transient simulation output is shown in Figure 2 and 3. The instantaneous amplitude of the pulse Vdiff at the time of effective clock decides the output pulse polarity with a negation. The output was observed to remain 0 for 3.53 s even after the clock became effective. This type of latency was observed at the time of measuremnet as well and discussed in Sec. 3. The effect of slewrate 05 V/s can be observed in the plot with a slow rise time. It can be observed from the plot the output voltage takes expected slewtime of 4 s to rise from 0 to 2 volts. To have a good pulse shape either slewrate has to be increased or clockrate has to be decreased. Figure 3 shows a better output pulse for a reduced clockrate.
2.00
Vout
2.00
0.00
random data. This gives datarate as: 8/11 Mbps=727 Kbps. The microcontroller current was measured at the power measurement jumper and was found to be 1332 ÂµA. This gives the power consumption as: 2.68 VX1332 ÂµA=3.57 mW. The
ClockN
Clock
3.00
3.00
0.00
performance of the circuit may further be improved by use of integrated resistors and design optimization. Application specific design optimization of a Schmitt trigger circuit is getting attention in recent days [31]
200.00n
Vdiff
200.00n
0.00 15.00u 30.00u 45.00u 60.00u 75.00u 90.00u
Time (s)
A low volume of data of 2368 bits was collected, as automated setup was not ready. The data was analyzed with NIST test suite [25], the present statistical test suite to certify the unpredictability of the data. 12 out of 17 tests were done. Only those tests that need sequence length less than 2368 were done. The test suite was written in MATLAB and was tested for sequences with predictable results. These test sequences were: (i) 0000—, (ii) 11111–
— (iii) 1010—.
Table 4 shows that the data qualifies for NIST test. This certifies that, the low volume of data or
Figure 2. Simulation 1 for LM741
Vout
ClockN
Clock
2.00
2.00
0.00
3.00
3.00
0.00
IEEE Trans. Appl. Supercond., vol. 21, pp. 843 – 846, June 2011.

J. M. Segui, J. G. Alfaro, and J. H. Joancomarti, A Practical Implementation Attack on Weak Pseudorandom Number Generator Designs for EPC Gen2 Tags, in Proc. Wireless Personal Communications, July 2011, pp. 1 17.

P. PerisLopez, E. S. Millan, J. C. A. V. Lubbe, and
L. A. Entrena, Cryptographically Secure Pseudo
Vdiff
200.00n
Random Bit Generator for RFID Tags, in Proc. ICITST10, Nov. 2010, pp. 490495.
200.00n
0.00 50.00u 100.00u 150.00u 200.00u
Time (s)

S. A. Wilber, "Random number generator and generation method", U.S. Patent No. 7752247 B2, 2010.
Figure 3. Simulation 2 for LM741


Conclusion
A true random number generator was implemented with a dualsupply operational amplifier. This was also implemented with the singlesupply operational amplifiers of an MSP430 microcontroller, used widely for RFID tags. The random thermal noise voltage of the resistors at the input of an onoff mode positive feedback operational amplifier in the Schmitt trigger configuration was utilized to generate the random numbers. The data passed the NIST test, the test of unpredictability. Due to moderate power consumption and low datarate, the data is suitable as a seed value for a pseudorandom number generator.

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TABLE 1. FEATURES OF RECENTLY PROPOSED PSEUDO RANDOM NUMBER GENERATORS
Infor mati on sourc e 
Working principle 
Any particular drawback 
Attack immune ? 
NIST test results 
Imple mente d in embe dded? 
Imple mente d on Si? 
Data rate 
Power consumpti on 
[3] 
Reseeding mixing PRNG 
Requires seed values 
No 
17 out of 17 passed 
No 
No. Only simula tion 
6.2 Gbps 
13.9 mW@200 MHz, estimated 
[4] 
PRNG of MIFARE tags 
Requires seed value 
No 
17 out of 17 passed 
Yes 
No need 
127 KBps 
Not known 
[5] 
PRNG using complex logic 
Requires seed values 
No 
Passed. Not shown 
No 
No. Only simula tion 
~100 Kbps 
~250 nW, estimated 
[7] 
A PRNG with a TRNG for seed value 
— 
No 
14 out of 17 done, 1 failed 
Yes 
No need 
Not known 
Not known 
[8] 
A PRNG using Blum Blum Shub algorithm 
Requires seed values 
No 
No 
Yes 
No need 
97 Kbps 
Not known 
[11] 
A PRNG using mathematical functions 
Requires seed values 
No 
No 
No 
No 
Not known 
Not known 
[13] 
A PRNG based on differential current mode chaos 
Requires seed values 
No 
Not done 
No 
Yes 
Not known 
0.8 mW 
TABLE 2. FEATURES OF RECENTLY PROPOSED TRUE RANDOM NUMBER GENERATORS
Infor mati on sourc e 
Working principle 
Any particular drawback 
Attack immune ? 
NIST test results 
Imple mente d in embe dded? 
Imple mente d on Si? 
Data rate 
Power consumpti on 
[1] 
Telegraphic random noise based TRNG in a CRRAM. 
Bit pattern is sensitive to voltage drop across CRRAM. 
No 
6 out of 17 done and passed 
No 
Yes 
~Kbps 
Not known 
[6,
12] 
TRNG by thermal noise detection in SFQ circuit 
Maintenance of superconductive temperature 4,2 0K. Not portable. 
No 
11 out of 17 done and passed 
No 
No. Only simula tion 
30 Gbps 
Not known. It must be very high for temperatur e maintenan ce 
[14] 
A TRNG with a metastability based quality control 
Initialization time may be very high 
Yes 
7 out of 17 done. Tests pass at a lower efficiency 
No 
Partly 
200 Mbps at the highest efficienc y, does not pass NIST 
Not known 
[16] 
A TRNG based on MOS at soft breakdown 
May drift to permanent or no breakdown 
No 
Not shown 
No 
No 
50 Kbps 
Not known 
[17] 
A TRNG based on direct amplification of thermal noise and further randomization 
Direct amplification introduces deterministic noise 
No 
Not done 
No 
Partly 
40 Mbps estimate d 
3.6 mW estimated 
This work 
A TRNG where instant polarity of themal noise decides the bits 
— 
Yes 
12 out of 17 done and passed 
Yes, MSP4 30 in WISP tag 
No need 
727 Kbps 
3.57 mW 
PERATIONS
TABLE 3. SEQUENCE OF OPAMP O *
Time slot in 5.5 ÂµS 
1 
2 
3 
4 
5 
6 
7 
8 
Opamp 1 
+ FB 
+ FB 
Off 
– FB 
– FB 
Off 
+ FB 
+ FB 
Opamp 2 
– FB 
Off 
+ FB 
+ FB 
Off 
– FB 
– FB 
Off 
Opamp 3 
Off 
– FB 
– FB 
Off 
+ FB 
+ FB 
Off 
– FB 
*Positive (+), Negative (), and feedback (FB)
TABLE 4. NIST TEST RESULTS*
Test 
Recommended input size 
Input size 
No. of sets 
p_value pass percentege 
Frequency (monobit) 
Sequence length n100 
n=100 
23 
100 
Frequency within a block 
Block length M20, block no. N<100, sequence length n=MN100, M>0.01n 
n=100, M=20, N=5. 
23 
100 
Runs 
Sequence length n100 
n=100 
23 
100 
Longest run 
Sequence length, n=128, block length, M=8 
n=128, M=8 
18 
100 
Binary matrix rank 
No. of blocks N38 
N=38, 2X2 matrix, n=152 
15 
100 
Dicrete Fourier Transform (spectral) 
Sequence length n1000 
n=1024 
2 
100 
Nonoverlapping template matching 
No. of blocks N100. Template size m=9 or 10 
Blocklength M=70, N=1, m=9, n=70 
33 for each template. Total template=148 
98.64100 for 148 p_values Threshold 95.43 
Serial 1 
Block length m[log2n]2. 
n=16, m=2. 
148 
99.32. Threshold 91.53 
Serial 2 
95.95 Threshold 91.53 

Approximate entropy 
Block length m<[log2n]5. 
n=65, m=1 
36 
100 
Cusum forward 
Sequence length n100 
n=100 
23 
100 
Cusum backward 
*p_value0.01 to pass