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 Total Downloads : 451
 Authors : Nivedita. J, Venkatesan. K
 Paper ID : IJERTV2IS4720
 Volume & Issue : Volume 02, Issue 04 (April 2013)
 Published (First Online): 25042013
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
VLSI Architecture For Area And Power Optimized Spectrally Efficient FDM Transmitter
1 Nivedita. J, 2 Venkatesan. K
1PG Scholar, Department of Electronics and Communication Engineering, Sri Shakthi Institute of Engineering and Technology, Coimbatore
2Assist. Prof. ECE, Sri Shakthi Institute of Engineering and Technology, Coimbatore
Abstract
Spectrally Efficient FDM employs nonorthogonal overlapped carriers to improve spectral efficiency for future communication systems. Nonorthogonal multicarrier systems achieve spectral savings by either reducing the spacing between the subcarriers in frequency or transmission time. But the loss of orthogonality complicates both signal generation and detection. SEFDM signal shall be realized with standard IDFT blocks judiciously arranged for SEFDM modulation. A VLSI architecture based on multistream FFT, which offers substantially reduced circuit area and power is used this work.
KeywordsBandwidth efficiency, multicarrier modulation, transmitter, wireless communications.

Introduction
The ever growing demand from the wireless communications has always inspired the research for techniques to save the spectrum and combat wireless channel impairments. Spectrally efficient frequency division multiplexing (SEFDM) system promises better utilization of bandwidth by reducing the spacing of subchannels. The first systems to appear were Fast OFDM (FOFDM) [1] and mary amplitude shift keying OFDM (MASK) [2], both of which halve the spectrum utilization, but are constrained to one dimensional modulations such as BPSK and Mary ASK. All variants of SEFDM systems are basically multicarrier modulation schemes that multiplex non orthogonal overlapped subcarriers. Following this, came spectrally efficient FDM (SEFDM) [3], high compaction multicarrier communications (HCMCM) [4], overlapped FDM (OvOFDM) [5] and multistream faster than Nyquist signalling (FTN) [6][8] all of which promote variable spectral utilization savings for two dimensional modulations. In
principle, nonorthogonal multicarrier systems achieve spectral savings by either reducing the spacing between the subcarriers in frequency and/or transmission time, thus, communicating information at a faster than Nyquist rate.
Despite the favourable spectral savings on offer, in practice, the loss of orthogonality complicates both signal generation and detection. For the detection, Maximum likelihood (ML) is suggested as the optimum technique in additive white Gaussian noise (AWGN) channels[1]. Nevertheless, ML detection is overly complex, with a computational complexity that grows exponentially with the size of the system.
As for the generation of SEFDM modulated symbols, the SEFDM signal can be realized with a similar complexity to OFDM system[14], by utilizing standard inverse discrete Fourier transform (IDFT) blocks, judiciously arranged for SEFDM modulation. Minor modifications on the input streams are needed and the designs rely mainly on standard IDFT operations that can be efficiently realized with the inverse fast Fourier transform (IFFT) algorithm.
In this paper, we introduce a VLSI architecture based on the FFT, which offers substantially reduced complexity analysis. The FPGA implementation is intended for use in an SEFDM performance evaluation test bed to further enable practical demonstration of the spectrally efficient physical layer.

The SEFDM System
SEFDM signal is constructed by modulating a block of the input data stream on parallel carriers, as shown in Fig1. The carriers in FDM systems are spaced by a fraction of the inverse of the symbol duration, violating orthogonality condition of OFDM systems where the spacing is inversely proportional to the symbol duration. The distance between the carriers in frequency, denoted by f is given by f = /T where is BW compression and T is duration of one SEFDM symbol. SEFDM signal is generated using a bank of modulators that generates the sub carriers. It requires high frequency precision in order to reduce frequency offset effects. Each of the N complex input symbols modulates one of the nonorthogonal and overlapping subcarriers, hence, giving the SEFDM signal x (t) as
X(t)= (1)
The preceding analysis in AWGN channels is included here as a general introduction to SEFDM system performance. Notwithstanding, the effects of frequency selective fading are of key significance and transmission over different fading channel conditions is an important area of study for wireless systems.
Fig.1 SEFDM block diagram

The IDFT Design of SEFDM Signals

General Description
In analogy to OFDM, it is shown that the SEFDM signal can be expressed by IDFT operations. It is shown that there are ways to express the SEFDM signal with an IDFT operation with simple manipulations of the input symbol vectors. These manipulations are merely in the form of zero insertions either at the end of the vector only, in a manner similar to zero padding and/or between the symbols. The change in length ensures the alignment of the IDFT frequency samples and the SEFDM subcarriers and the zeros suppress the unwanted frequencies.
The samples of the SEFDM signal can be generated using c IDFT operations each of length of N points. The input symbols are padded with (c1) N zeros and then arranged as a matrix in column major order. An IDFT operation is then performed on each row. The signal is finally composed by combining rotated versions of the IDFT outputs as depicted in Fig3.
Fig.2 Generating SEFDM signal based on a single IDFT operation
For integer values of N/ (i.e., (N/) ), the work in shows that a discrete SEFDM signal X (k) can be described as
X = , for k=1…N1 (2) Where
= {}
and . is the N/ point IDFT of the
argument, with being a vector of length N/ , whose elements take the values of either input symbols or zeros as


VLSI Architecture

SEFDM Transmitter
The SEFDM signal is composed of a combination of symbols each modulated on
= (3)
= (3)
, 0 < < 0, < N/
Fig.3 SEFDM IDFTbased transmitter with multiple IDFT operations
Thus the SEFDM signal can be realized with a single IDFT block, with a length longer than N. The SEFDM transmitter in this case depicted in Fig2. Furthermore, it is shown in that by expressing the term as a rational number, that is by taking = /, where both b and c are integers and c, the SEFDM signal can be expressed as
one of the subcarriers. Therefore, the conventional SEFDM transmitter consists of a bank of modulators running at the subcarriers frequencies as can be seen in Fig3

Zero Insertion and Reorder
Fig4 illustrates the general symbol reordering operation, which consists of padding the input symbols with (c1)N zeros before arranging them as a Ã— N matrix in column major order. A implementation of this operation implies a buffer of complex words to hold the sparse complex matrix. However, since each incoming symbol is mapped to only one IFFT input, it is only necessary to use a multiplexer in front of each IFFT to choose either the incoming si symbol or 0+ j0 samples.
1 1
2
X (k) = =0
(4)
As for the case above, here we define to be a vector of length cN whose element take the values of either the input symbols
/ or zeros as
Fig.4 General Operation of symbol reordering

Parallel IFFTs
The N point IDFTs are implemented in
=
/
,
(5)
this section as N point IFFTs, which can be implemented as parallel IFFT blocks. Using
0,
and I = {0,b,…,b(N1)}. The equation (10) can be rearranged as,
parallel IFFTs allows the highest throughput and constant latency independent of , at the cost of linear increase in area and power. Here used 16point, 8bit complex IFFT blocks based on radix22 flow graph. The IFFTs have
1 1
2
1
2
an enable signal which when deasserted
X(k)= =0
=0 +
(6)
gates the internal clock and clears the output
By substituting with n= + .
registers to zero.

Postprocessing
The post processing operation combines the parallel IFFT outputs after multiplication with a complex exponential in order to produce the discretetime output samples, Xk. The complexity of the post processing is linear functions of c, where we require (c1) complex multiply accumulate (CMAC) operations. The hardware required includes the CMACs and LUTs to store precalculated rotation coefficients in readonly memory (ROM).
4.2 Whole Trellis Stage Pruning for /
In this case, the reordered zero bins Fig.4 are arranged in a compact manner such that nonzero bins are followed by at least 2 contiguous zeros. Hence, the first IFFT trellis stage contains only half BFs and can be pruned entirely up to the input to the first complex multiplier, removing . ( 2) BF operations and . 2 complex words of storage. Fig6 shows the IFFT signal flow graph for = 1/2, showing the gray edges which are redundant. Unfortunately, as previously mentioned, bandwidth compression ratios less than 1/2 incur a BER penalty and hence this optimization is only really applicable to = 1/2 , at least in this particular application.
Fig.5 Partially pruned half BFs occur when one of the complex inputs is zero
Fig.6 IFFT signal flow graph for = 1/2, N=16



Implementation Results
The proposed architecture has been implemented in VHDL and verified using ModelSim simulator. IDFT core was generated by the Xilinx LogiCORE IP inorder to optimize this block and also the clock period of 4ns was achieved. The results are shown below.
Fig.9 Output of SEFDM Transmitter

Conclusion
The newly developed SEFDM system is described. These results demonstrate that a reconfigurable SEFDM transmitter can be realistically implemented with a modest increase in circuit area and power dissipation when compared to conventional OFDM.
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