Tunneling Transistor based 6T SRAM Bitcell Circuit Design in Sub-10nm Domain

Tunneling Transistor based 6T SRAM Bitcell Circuit Design in Sub-10nm Domain

Namgiri Snehith, M Indu Chowdary, Maaddamsetty Sai Bhavana, Danduboyina Jyoswitha Sindhu.

Department of Electronics and Communication Engineering, Koneru Lakshmaiah University.

AbstractThe Static Random Access Memory (SRAM) directly impacts the performance of the modern multi-core processor. Hence, the power, performance and area metrics are very crucial for SRAM design. In this article, we have successfully designed 10 nm TFET based 6T SRAM circuit at reduced supply voltage of 0.5 V. We also have optimized the circuit for high density, high performance, intermediate (trade-off between high density, high performance) 6T SRAM application. Later, we have estimated the dynamic Read power, Read energy, Write power, Write energy. The performance metrics: Read delay and Write delay are also analyzed precisely. These power, energy, delay metrics are also compared against the existing 10nm FinFET.

Index Terms Tunneling, TFET, 6T SRAM, Dynamic Read and Write Power.

I. INTRODUCTION

Nonstop scaling of silicon CMOS device has led to a record increase in multi-core performance of latest microprocessors. Because of the exponentially growing transistor count, the total power consumption and energy efficiency are important matrix for today's multi-core microprocessors. Therefore, nanoelectronics enabled energy efficiency at the device, circuit and system level are crucial. The dynamic power depends on the square supply voltage. Supply voltage cut while upholding device performance is an efficient method to decrease the power consumption because it decreases the dynamic power quadratically and the leakage power linearly. The fall of the threshold voltage leads to IOFF rise exponentially for MOSFET The fundamental limit of MOSFET threshold voltage scaling blocks the supply voltage scaling. Hence, the supply voltage restricts the ION and ION/IOFF ratio. In MOSFETs, the theoretical restriction of 60 mV/decade sub-threshold swing at room temperature leads to limit the threshold voltage scaling and low power operation [1].

The organization of the paper is as follows. Section I illustrates the limitation of the existing Silicon based MOSFET technology. Section II provides benchmarking for emerging devices. It also illustrates benchmarking of exiting TFET technology. Section III represents the simulation, result and analysis. Section IV shows the benchmarking between TFET and FinFET. Finally, Section V concludes the paper with a brief of future work.

application. Benchmarking on post-CMOS logic transistors is summarized in [4]-[5]. Table 1: Performance Benchmarking for Emerging Devices

Table 1: Performance Benchmarking for Emerging Devices [4].

1. State of Art of Tunnel FET

   The device performance of n-type III-V Tunnel FET is summarized in Table 2.

   Table 2: Performance Comparison for fabricated III-V TFETs.

   1. RESULT AND ANALYSIS

      1. Simulation Setup

         A Verilog-A lookup table based 10nm TFET transistor model is used for the simulation. This model is not optimized and affects the Write operation significantly. But this is the best TFET model available to design circuit. This 6T SRAM circuit is designed and simulated by HSPICE.

      2. 6T SRAM

Figure 1 shows TFET based 6T SRAM, which is most popular high density SRAM circuit. The operation of 6T SRAM is available in for interested readers.

II. EXISTING TFETS

A. Why Tunnel FET?

Numerous novel transistors have been explored to reduce power consumption for emerging circuit and architecture

1. Read Operation

   Figure 2 shows the Read operation of TFET based 6T SRAM.

   Figure 3 shows the Read operation output of 10nm TFET based 6T SRAM when PU:PD:PG ratio is 1:1:1, initial condition and final condition.

   Figure 4 shows the Read operation output of 10nm TFET based 6T SRAM when PU:PD:PG ratio is 1:5:2, initial condition and final condition.

   Figure 5 shows the Read operation output of 10nm TFET based 6T SRAM when PU:PD:PG ratio is 2:5:2, initial condition and final condition.

2. Write Operation

Figure 6 shows the Write operation of TFET based 6T SRAM. This Verilog-A lookup table based 10nm TFET transistor model [2] has couple of limitations: (i) it give huge nose to Q and QB after Write operation for any circuit combination; (ii) it does nt allow 6T SRAM circuit design for most of the sizing. We have optimized our 6T SRAM circuit to minimize these unwanted glitches from the TFET.

Figure 7 shows the Write operation output of 10nm TFET based 6T SRAM when PU:PD:PG ratio is 1:1:1, initial condition and final condition.

Figure 8 shows the Write operation output of 10nm TFET based 6T SRAM when PU:PD:PG ratio is 1:5:2, initial condition and final condition

Figure 9 shows the Write operation output of 10nm TFET based 6T SRAM when PU:PD:PG ratio is 2:5:2, initial condition and final condition

1. BENCHMARKING OF TFETVS.

   The comparison between 10 nm Tunnel FET 6T SRAM and 10 nm FinFET 6T SRAM is summarized in Table 3. The physical significances of the benchmarking between are discussed below.

   • The dynamic write power of TFET is 4.55E+06 times more than FinFET based SRAM. This a drawback of TFET device 6T SRAM.

   • The dynamic write energy of TFET based 6T SRAM is 4.09E+06 times more than FinFET based 6T SRAM.

   • TFET based 6T SRAM writes 11% faster than FinFET based 6T SRAM.

   • The dynamic Read power of TFET based 6T SRAM is

     8.29 E+06 times more than FinFET based 6T SRAM. This a drawback of TFET device 6T SRAM.

     TFET based 6T SRAM reads 21% slower than FinFET based 6T SRAM.

   • The dynamic Read energy of TFET based 6T SRAM is 1.01E+08 times more than FinFET based 6T SRAM.

   Table 3: Benchmarking between 10 nm TFET based 6T SRAM and 10 nm FinFET based 6T SRAM.

2. CONCLUSION AND FUTURE WORK

We have successfully optimized our 6T SRAM circuit to minimize these unwanted glitches from the TFET model. The read and write operation are ensured with enough glitch margin. The only bright side is TFET based SRAM writes 11% faster than FinFET based SRAM. TFET based 6T SRAM reads 21% slower than FinFET based 6T SRAM. So, the speed matrix of TFET SRAM is ok. But the dynamic Write power, dynamic Write energy, dynamic Read power and dynamic Read energy of TFET based SRAM are more than FinFET based SRAM. So, TFET based 6T SRAM is more power hunger than FinFET based 6T SRAM. Our future work will involve the detailed analysis of TFET based SRAM.

REFERENCES

[1] Jawar Singh, Ramakrishnan Krishnan, Saurabh Mookerjea, Suman Datta, Vijaykrishnan Narayanan, TFET based 6T SRAM cell, Patent: US 20120106236 A1.

[2] Huichu Liu, Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta, III-V Tunnel FET Model, nanoHUB, 2015. doi: 10.4231/D30Z70X8D.

[3] Zhou, G. et al, "InGaAs/InP tunnel FETs with a subthreshold swing of 93 mV/dec and ION/IOFF ratio near 106," IEEE. Elec. Dev. Lett., vol. 33, no. 6, p. 782-784, 2012.

[4] Dmitri E. Nikonov and Ian A. Young, "Uniform methodology for benchmarking beyond-CMOS logic devices," in IEEE IEDM Tech. Dig., p.25.4.1-25.4.4, 2012.

[5] Huichu Liu, Suman Datta, Vijaykrishnan Narayanan, Steep Switching Tunnel FET: A Promise to Extend the Energy Efficient Roadmap for Post-CMOS Digital and Analog/RF Applications, IEEE International Symposium on Low Power lectronics and Design (ISLPED), pp. 145-150, 2013.

[6] Chih-Cheng Hsiao, 6T SRAM cell, Patent: US 20160111145 A1. [7] Huai-Ying Huang, Yu-Kuan Lin, Sheng Chiang Hung, PingWei

Wang, 8T low leakage SRAM cell, Patent: US 7773407 B2.