 Open Access
 Total Downloads : 460
 Authors : Md Yaseen, Dr. P Usha
 Paper ID : IJERTV4IS060912
 Volume & Issue : Volume 04, Issue 06 (June 2015)
 DOI : http://dx.doi.org/10.17577/IJERTV4IS060912
 Published (First Online): 01072015
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Transformerless High Gain Boost Converter for Low Power Applications with Feedback Control
Mr. Md Yaseen
PG Scholar, M.tech (Power electronics) EEE Department,
Dayananda Sagar College of Engg.
Bangalore, India
Dr. P. Usha
Professor, EEE Department, Dayananda Sagar College of Engg.
Bangalore, India
AbstractAtransformerless boost converter which provides high voltage gain without utilizing transformer or coupled inductorsandextreme duty cycle is proposed in this paper. Also it is able to cancel the ripples in the input current at a preselected duty cycle, without increasing the number of components.The converter combines the features of boost converter and a three switch high voltage converter. At the input side, two inductors are interleaved for cancelling the input current ripple and at the output side switched capacitor voltage multiplier is used to increase the voltage gain. Feedback control is used to make the output voltage constant in spite of variation in the input or load or both i.e. both line and load regulation is accompanied. This proposed converter configuration helps eliminate the input current ripple and voltage deregulation for low power applications.
KeywordsHigh gain boost converter, input current ripple cancellation, line and load regulation.

INTRODUCTION
Renewable energy sources are gaining momentum for the generation of electricity due to the rapid depletion of fossil fuel reserves. Also continuous consumption of traditional fossil energy sources leads to global warming.The voltage obtained from these renewable energy sources is usually low in amplitude; hence a boost converter is needed to step up the voltage to the required level and alsoto drain a continuous current with minimum ripple. Line and load regulation is also an important factor in the low power applications. Therefore this converter is more feasible for these applications.
Several other topologies have been proposed which includes the use of a coupled inductor and/or transformer, switched capacitor converter, zeta converter, bridge converter etc.
The use of couple inductors sometimes induces high voltage spikes across the switch, because of the resonance between leakage inductance and parasitic capacitance which is caused by the leakage inductance energy [1]. A clamp circuit is used to recycle the leakage inductance energy in the coupledinductor boost converter reducing the voltage stress on the switch [2]. In the capacitordiode clamped circuit, the leakage energy is recycled in the similar way without utilizing an additional switch [3]. The use of ZCS and/ ZVS technique with coupledinductors and transformers is presented in [4]. In
this switches turned on at zero voltage and turned off at zero current. The paper presented in [5], uses coupled inductor and voltage lifting technique to achieve a high voltage gain. In [6], a switched coupledinductor boost converter is presented where the leakage energy is recycled by a series diode in parallel with the basic boost converter diode. The converter presented in [7] uses coupled inductor and switched capacitor technique for a flyback converter. The coupledinductor transfers the energy to load or capacitor and leakage energy is recycled. The switched capacitor increases the voltage gain. Similar technique is used in [8].The converter in [9] is a nonisolated high gain boost converter based on half bridge converter; it combines features of boost converter and a half bridge converter with voltage doubler rectifier. In [10] and [11] integrated coupledinductor and voltage doubler technique is used to achieve a high voltage gain. Converters with only switchedcapacitors (without coupledinductors) are suitable for low power applications mainly because of switching frequency limitation and current spikes in the capacitors. Converters presented in [12] and [13] which are based on Switchedcapacitor achieve a high voltage gain. For high power applications, converters which do not use transformer or coupledinductor are presented in[14], [15], and [16] which are based on switchedcapacitor concept. Switchedcapacitor with complete charge interchange presented in [17], is not used in voltage regulation since it compromises the converters efficiency. Switchedcapacitor with complete charge interchange and Pulse width modulation presented in [18] provides voltage regulation. In renewable energy applications, converter must also drain continuous current with minimum ripple in the current.
The proposed converter combines complete charge interchange switched capacitor with a boost converter into a single converter. Herein, the input current ripple is removed by interleaving two inductors at the input side and voltage gain is increased by using switchedcapacitor multiplier at the output. A small inductor is used to limit the peak current due to switching process which minimizes the current spikes in the circuit. Feedback control is used to control the duty ratio of the switches make the output voltage constant in spite of variation in the input or load or both i.e. to provide both line and load regulation.

DESCRIPTION OF THE PROPOSED CIRCUIT
The circuit diagram of the proposed converter is shown in Fig. 1, the proposed converter is composed of a voltage regulator and a hig gain boost converter. Voltage regulator is used to regulate the solar panel output and is fed to the high gain boost converter. The high gain boost converter consists of two switches S1 and S2, three diodes D1, D2 and D3, three capacitors C1, C2, C3 and C4, and two inductors L1 and L2 and a small inductor L3 to limit peak current. L3 is chosen very small typically 50 times smaller than L1.
Fig. 1 proposed converter

OPERATING PRINCIPLE
In order to illustrate the operation of the proposed converter, several assumptions are made:

All switches are ideal.

The two inductors L1 and L2are large enough to be consideredas a constant current source during a switching period.

The output capacitor C4is large enough to be considered as a constant voltage source of Vin/( D * (1 D)).

All the switches are MOSFETs with parasitic
diodes.
The two switches S1 and S2 are complementarily,

when S1 is ONN, S2 is OFF and when S2 is ONN, S1 is OFF. The switching time is Ts, and D is the duty ratio for S2. Therefore S2 is conducting for a period DTs and S1 for (1 D)Ts.
Mode 1: When the switch S1 is on i.e. during (1 DTs) period, the equivalent circuit is shown in Fig. 2.Inductor L1 starts charging with negative polarity at diode D1 thus reverse biasing the diode D1 and blocking voltage across capacitor C1. Current through L1 rises with a slope VIN/L1. Also diode D3 is reverse biased blocking voltage across C3. Since the switch S2 is open, L2 forces the diode D2 to turn on. Current through L2 discharges at the rate (VIN – VC2)/L2 charging capacitor C2.
Fig 2. Equivalent circuit when S1 is conducting
Mode 2:When S2 is ON (and S1 is OFF) during DTs period, the equivalent circuit is shown in Fig. During this period, L1 forces diode D1 and D3 to turn on. Current through L1 discharges at the rate (VIN – VC1)/L1 charging capacitor C1. While S2 is conducting D2 is turned off, inductor L2 stores energy and current through L2 rises with a slope VIN/L2 since S2 is ON.During this period, capacitor C2 and C3 are connected in parallel forming a switched capacitor type circuit. Therefore L3 is used to limit the peak current in the circuit.
Fig 3. Equivalent circuit when S2 is conducting
<>Clearly, from the operation of the proposed topology, the input current is sum of currentsthrough L1 and L2. Since L1 and L2 charge and discharge complimentary, the size of the inductors are chosen such that the input current is ripple free at a selected duty cycle.
When the load is connected to the converter, the output voltage also varies with the change in the load. Hence feedback is provided to maintain constant voltage across the load in spite of variation in load.
Fig 4. Feedback model of Simulink
The Feedback is given to the Psim model of the proposed converter as shown in fig 5


DESIGN CONSIDERATION
The voltage regulator is a simple boost converter, the output voltage for this is given by
= . . . . . (1) 1
Vin output of voltage regulator Vsolar input from solar panel Db Duty ratio of boost converter
The output of voltage regulator, Vin is given as input to the high gain boost converter.
Since the state variables of L1, L2 and C1 have triangular waveform similar to traditional converters, their dynamics are analyzed by considering their average behavior. While L3, C2 and C3 form an switched capacitor type circuit, hence their dynamics is calculated with additional consideration.
Converters duty ratio d(t) is defined as percentage of time over the switching period that switch S2 is closed,
1 +
Fig 5. Feedback for the converter
= 2 . . . . . . . . . . (2)
The output voltage from the load is added to the required reference voltage (with gain 1) by using sum block sum1. The error is limited between a maximum and minimum value using limiter, lim1 and is multiplied with gain k. This error value is chosen as outlink node (Dout) from the psim model and is added with the previously stored error value in the memory block by the adder block of the Simulink control loop. The sum value of the adder block is given as inlink node (Din) to the PSIM model. Then, this value from the adder block (in the Simulink control loop) is added with a constant value VDutycycle(which determines duty cycle) by the sum block sum2. The output of sum block 2 is given to the noninverting terminal of the comparator, comp2 after passing through the limiter, lim2. To the inverting terminal of the comparator a reference sawtooth voltage is given. Upon comparing the two signals the comparator generates a unity magnitude voltage pulse whenever the input at non inverting terminal is higher than inverting terminal. This voltage pulse is given to the switch S1 directly through the ONOFF switch. The output of comp2 is inverted using a NOT gate and is given to switch S2 through the ONOFF switch.
If the output voltage changes due to change in the load then, the duty cycle is controlled to maintain required constant voltage across the load.
Ts switching period
q2 switching function – is equal to one when S2 is closed and zero when S2 is open.
Voltage across L1 and L2, neglecting ESR is given by
1 1 = 1 + 1 . . . . (3)
2 2 = + 1 2 . . (4)
Under steady state average voltage across inductor is zero. Equating LHS of (3) and (4) to zero
1
1 = . . . . . . . (5)
2 = 1 . . . . (6) (1 )
Clearly from the above equations, Vc1 and Vc2 are proportional to each other,
1 = 1 2 . . . . . (7)
2 =
(1 )
1 . . . . . (8)
Current through capacitor C1 is given by
1 1
1 + 3
Where RL2 is ESR of L2.Under steady state, the average
= 1 (
). . .. (9)
voltage across inductor is zero.
In steady state, average current through capacitor is zero. Equating LHS of 9 to zero, we get
0 = 2 2 + 1 2 2 2
= 2 2 1 2 . . (21)
1 = 1
1 + 3
. . . . . . (10)
Substituting (16) in (21)
Since C2 and C3 form an switched capacitor type circuit,
2 = 1
. . . . (22)
therefore average dynamics is not be applied. Average Current through L2 is calculated by considering input
(1 ) + 2
1
output power balance.
Substituting (12), (19) and in (22) in (13)
2 = 1
1 + 3
1 1
1
. . . (11)
= + 1 + (1 ) + 2
(23)
Since C2 and C3 form an switched capacitor type circuit
1
1
C2 clamps the voltage across C3, and both feature same voltage.
2 = 3 . . . . . (12)
The output voltage is
= 1 + 3 . . . .. (13)
Substituting (5), (6) and (12) in (13) we get
The voltage gain for various values of duty cycle has been performed and is shown in Fig. 6.
Clearly from the graph, voltage gain is minimum at D=50% and increases as D varies from 50%.
= 1
. . . . (14)
(1 )
Substituting (7) and (8) in (10) and (11), IL1 and IL2 can be given by
) =
1 = (1 + 1 1 1 ) 1
(15)
Gain
1 (1
)
2 = (1 + 1 1
2 = 1
) 2 . . (16)
1 (1
Duty cycle
Considering the ESR of L1, inductor L1 voltage is given by
1 1 = 1 1 1
+ 1 1 1 (17)
Where RL1 is ESR of L1.Under steady state, the average voltage across inductor is zero.
0 = 1 1 1 + 1 1 1
= 1 1 1 . .. . (18)
Substituting (15) in (18)
1 1
Fig.6 voltage gain vs duty cycle.

Inductor L1 and L2 sizing:
When S1 is closed i.e. during (1 D)Ts, voltage across L1 is equal to Vin.
1 =
1 1 =
1 =
1
= + 1 . .. (19)
1
Similarly Considering the ESR of L2, inductor L2 voltage is given by
2 21 = 2 2
1 = 1 . . . . (24)
1
When S2 is closed i.e. during (DTs), voltage across L2 is equal to Vin.
2 =
+ 1 2 2
2 (20)
2
2 =
2 =
This may lead to high current that rises above the peak
2 =
2
. . . . (25)
2
current limit and may destroy the other devices in the circuit. Hence L3 has to be introduced with proper design. Ceq is capacitance of series C2 and C3. Since L3 is very small it charges and discharges completely in a switching
The input current ripple is the difference between the two inductors current ripple.
cycle limiting the peak current as shown in fig 7 (b).It generates peak resonant at a frequency fo given by
1
= = 1
. . . (31)
=
2
1
. . . . (26)
2
2 (3)
The input current ripple can be eliminated by making LHS of (26) to zero, we get
2 = 1
1
. . . . . (27)

Peak current limiting inductor L3 sizing:
When S1 is open, D3 connects C2 and C3 in parallel, hence a inductor is needed to limit the current. The average current through diode is same as load current but shape may be undesirable, hence it has to be controlled.When S2 is closed C2 and C3 are connected in parallel and both will have same voltage. Let this be Vc.0. when S2 is opened for (1 D)Ts period, they are no longer connected and C3 discharges following the load current and C2 charges following current through L2. Let final voltages across C2 and C3 be Vc2.1 and Vc3.1 can be expressed as
2.1 = . 0 + 2 = . 0 + 2 1 (28)
2
3.1 = . 0 3 = . 0 1 (29)
3
At the end of (1 D)Ts, the voltage difference between C2 and C3 is given by
= 2 + 3 = 2 + 1 (30)
Fig.7 (b ) waveform for reactive components
The converter operates at a duty cycle D> 50%, hence L3 should be selected such that fo>Fs.
Fs switching frequency
The peak current through L3 is given by
3 = . . . . (32)
3

Capacitor:
2 3
In the absence of peak limiting inductor in series with D3, peak current would be Vdiff over resistance in the loop, on state resistance of S2 and D3 and ESR of C2 and C3. This has been shown in fig. 7 (a)
When S1 is closed, current through C1 follows load current, therefore
1 = 1 . . . . (33)
1
When S1 is closed, C2 charges following current through L2, therefore
2 = 2 1 . . . . (34)
2
When the current through L3 rises above load current then C3 starts charging with increased voltage 3 given by
/3. The time while C3 is charging is the time when io
<iL3(t). C3 discharges through the remaining time of the switching period, therefore
Fig.7(a) equivalent circuit
= ( 1
2
2
arcsin . . (35)
3
Vsolar, Vsw1)
Tdis time in which C3 discharges. During this period, C3 follows load current hence
3 = . . . . (36)
3


SIMULATION
Vgb
ThePsim model of the proposed converter integrated with Matlab Simulink control loop is shown in Fig 8. The simulation of the Model using Matlab 2008 and Psim 9.1 is discussed in this chapter in various sections.
Time (in seconds)
Fig.9(a)Vsolar, sw1 and Vgb
Fig. 8 Psim model of the proposed converter
Vin
Parameter
Value
Vsolar
10
L
150 uH
C
220 uF
Vin
16
Duty cycle, D
82.5%
L1
100 uH
L2
470 uH
L3
6 uH
C1, C2 & C3
10 uF
C4
100uF
Fs
25 kHz
The converter is simulated for a period of 1 second with the following parameter values.
The input from solar panel is measured to be 10V. The waveforms for various voltages of voltage regulator are shown in fig 9(a).
Time (in seconds)
Fig.9(b)Vin
Vs = input voltage from PV cell
Vsw = reference sawtooth voltage 15v peak to peak and 25k frequency
Vgb = output of comp1 (voltage pulse to mosfet switch S).
The duty cycle, D is chosen 82.5%, and L1 is selected 100uH, from (27), we get
L2 = 470uH
The peak limiting inductor L3 is very small. Therefore L3
= 6uH is selected.
The output of sum block 2 is given to the noninverting terminal of the comparator, comp2 after passing through the limiter block, lim2. To the inverting terminal of the comparator a reference sawtooth voltage is given. The Comp2 generates a unity magnitude voltage pulse whenever the input at noninverting terminal is higher than inverting terminal. This voltage pulse is given to the switch S1 directly through the ONOFF switch. The output of comp2 is inverted using a NOT gate and is given to switch S2 through the ONOFF switch. This is shown in Fig. 10
VG1 (in volts)
VG2 (in volts)
IL1 (in Amp)
On the other hand, when S2 is closed Current through L2 rises with a slope VIN/L2, reverse biasing D2. While S2 is conducting, current through L1 discharges at a rate (VIN VC1)/L1 through D1 charging the capacitor C1. Furthermore D3 is forward biased and hence C2 and C3 are connected in parallel. Current through L1 and L2 is shown in Fig. 12.
Time (in seconds)
Fig.10 pulse signals to MOSFET switches
Current (in Amp)
The input current corresponds to the sum of current through L1 and L2. The inductors are selected such that both inductors are charged with same voltage. Since L1 and L2 charge/discharge in a complementary manner, the input current is ripple free as shown in Fig. 11. A small inductor L3 is used to limit the peak current when C2 and C3 are connected in parallel.
Time (in seconds)
Fig.11 input current
When S1 is closed Current through L1 rises with a slope VIN/L1 hence diode D1 and D3 are reverse biased, while S1 is conducting D2 is forward biased and Current through L2 discharges at a rate of (VIN – VC2)/L2 charging capacitor C2.
IL2 (in Amp)
Time (in seconds)
Fig.12 currentthroughinductors
Voltage (in volts)
When S1 is closed, diode D1 is reverse biased blocking the voltage across C1 and diode D3 is reverse biased blocking the voltage across C3 while L2 discharges charging the capacitor C2. On the other hand When S2 is closed, L1 discharges through D1 charging capacitor C1 and D2 is reverse biased. Furthermore while S2 is conducting D3 is conducts and therefore C2 and C3 are connected in parallel forming a switched capacitor type behaviour. The voltage across capacitor C1 and C2 is shown in Fig. 13.
Time (in seconds)
Fig.13 Voltage across capacitors
The output voltage Vo given by (26) is sum of voltage across C1 and C3, is shown in Fig. 14. Vo is measured to be 110V.
The converter is able to achieve zero ripples in the input current at a preselected duty cycle; it can be improved by designing optimal size of the inductors for a wide range of duty cycle.
Vo (in volts)
Time (in seconds)
Fig.14 Output voltage
An output capacitor C4 = 100 uF is used to remove the ripples from the output voltage.
Io (in Amp)
Time (in seconds)
Fig.15 load current
A resistive load R = 55 is connected across capacitor C4. Current drawn by the load is shown in Fig. 15
With the feedback, R can be varied between 5 to 550. If the output voltage falls or rises above the required reference value then the duty cycle is controlled using the feedback to the converter so that output voltage remains constant at 110V.
APPLICATIONS

Used in street LED lightening, 40100V.

Used in SMPS power supplies for Desktop, LED TV, LCD displays.

Used in Industrial control and Process control instrument set up.


CONCLUSION
The proposed converter uses solar energy as input and achieves a high voltage gain without utilizing extreme duty cycle. Also the converter is able to remove the input current ripple at a preselected duty cycle. Furthermore with the feedback, the converter is able to maintain constant output voltage if the output voltage changes due to change in the load i.e. load regulation. Also in this converter, smaller reactive components are used which has more advantages compared to the use of transformers.

REFRENCES

B. Axelrod, Y. Berkovich, and A. Ioinovici, Switched capacitor/ switchedinductor structures for getting transformerless hybrid DC DCPWMconverters, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 2, pp. 687696, Mar. 2008.

Y. P. Hsieh, J. F. Chen, T. J. Liang, and L. S. Yang, Novel high step up DCDC converter for distributed generation system, IEEE Trans. Ind.Electron., vol. 60, no. 4, pp. 14731482, Apr. 2013.

S. M. Chen, T. J. Liang, L. S. Yang, and J. F. Chen, A cascaded high stepup DCDC converter with single switch for microsource applications, IEEE Trans. Power Electron., vol. 26, no. 4, pp. 1146 1153, Apr. 2011.

B. R. Lin, J. Y. Dong, and J. J. Chen, Analysis and implementation of a ZVS/ZCS DCDC switching converter with voltage stepup, IEEETrans. Ind. Electron., vol. 58, no. 7, pp. 29622971, Jul. 2011.

T. J. Changchien, . K. Liang, J. F. Chen, and L. S. Yang, Stepup DCDC converter by coupled inductor and voltagelift technique, IETPower Electron., vol. 3, no. 3, pp. 369378, May 2010.

Y. Berkovich and B. Axelrod, Switchedcoupled inductor cell for DCDC converters with very large conversion ratio, IET Power Electron., vol. 4, no. 3, pp. 309315, Mar. 2011.

T. J. Liang, S. M. Chen, L. S. Yang, J. F. Chen, and A. Ioinovici, A single switch boostflyback DCDC converter integrated with switchedcapacitorcell, in Proc. 8th Int. Conf. Power Electron. ECCE Asia, May/Jun. 2011, pp. 27822787.

Y. P. Hsieh, J. F. Chen, T. J. Liang, and L. S. Yang, Novel high step up DCDC converter with coupledinductor and switchedcapacitor techniques, IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 998 1007, Feb. 2012.

K. B. Park, G. W. Moon, and M. J. Youn, Nonisolated high stepup stacked converter based on boostintegrated isolated converter, IEEETrans. Power Electron., vol. 26, no. 2, pp. 577587, Feb. 2011.

L. S. Yang, T. J. Liang, H. C. Lee, and J. F. Chen, Novel high step up DCDC converter with coupledinductor and voltagedoubler circuits, IEEE Trans. Ind. Electron., vol. 58, no. 9, pp. 41964206, Sep. 2011.

S. V. Araujo, R. P. TorricoBascope, and G. V. TorricoBascope, Highly efficient high stepup converter for fuelcell power processing based on threestate commutation cell, IEEE Trans. Ind. Electron., vol. 57, no. 6, pp. 19871997, Jun. 2010.

S. C. Tan, S. Bronstein, M. Nur, Y. M. Lai, A. Ioinovici, and C. K. Tse, Variable structure modeling and design of switchedcapacitor converters, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 9, pp. 2132 2142, Sep. 2009.

S. C. Tan, S. Kiratipongvoot, S. Bronstein, A. Ioinovici, Y. M. Lai, and C. K. Tse, Adaptive mixed ontime and switching frequency control of a system of interleaved switchedcapacitor converters, IEEE Trans. PowerElectron., vol. 26, no. 2, pp. 364380, Feb. 2011.

A. A. Fardoun and E. H. Ismail, Ultra stepup DCDC converter with reduced switch stress, IEEE Trans. Ind. Appl., vol. 46, no. 5, pp. 2025 2034, Sep./Oct. 2010.

S. Choi, V. G. Agelidis, J. Yang, D. Coutellier, and P. Marabeas, Analysis, design and experimental results of a floatingoutput interleavedinput boostderived DCDC highgain transformerless converter, IET PowerElectron., vol. 4, no. 1, pp. 168180, Jan. 2011.

B. Axelrod, Y. Berkovich, S. Tapuchi, and A. Ioinovici, Single stage singleswitch switchedcapacitor buck/buckboosttype converter, IEEETrans. Aerosp.Electron. Syst., vol. 45, no. 2, pp. 419430, Apr. 2009.

D. Gu, D. Czarkowski, and A. Ioinovici, A large DCgain highly efficient hybrid switchedcapacitorboost converter for renewable energy systems, in Proc. IEEE Energy Convers. Congr.Expo. ECCE, Sep. 2011, pp. 24952500.

S. BenYaakov, Behavioral average modeling and equivalent circuit simulation of switched capacitors converters, IEEE Trans. Power Electron., vol. 27, no. 2, pp. 632636, Feb. 2012.