Low Power and Low Area Digital FIR Filter Using Different Multipliers and Adders

DOI : 10.17577/IJERTV1IS3223

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Low Power and Low Area Digital FIR Filter Using Different Multipliers and Adders

T Ramesh Reddy, M. Tech Student, and Dr. K. Soundara Rajan, Professor

Depart ment of Electronics & Co mmunication Engineering Jawaharla l Nehru Technological Un iversity

Anantapur, India

Abstract-This paper imple ments low powe r dig ital Finite Impulse Response (FIR) filter re lying on radix four booth mu ltip lie r, seria l mu ltip lie r and serial adder and shift add mu ltip lie r. In this paper we consider mu ltiplie r and accumulate FIR filter architecture and fo lded transform of linear phase FIR filte r. These low power mu ltiplie rs and low power adders are used to reduce dynamic powe r consumption of digita l FIR filter.


    Dig ital signal processing (DSP) is used in wide range of applicat ions such as telephone, radio, video etc. Most of DSP computations involve the use of mult iply accumulate operations and therefore the design of fast and effic ient mult iplier impe rative. More ever, the demand for portable applications of DSP architectures has dictated the need for low power designs [1]. Digita l Fin ite Impulse Response filter has a lot of arithmet ic operations. In general, arithmet ic operation modules such as adder and mult iplier modules, consume much power, energy, and circuit area. Input bit width of the modules is quite important design parameter for lo w power. The power digital FIR filter circu it is reduced by optimization of taps and bit width of input signal and filters coeffic ients [2]. The dynamic switching power consumption of digital FIR filter is reduced by using data transition power diminution technique. This technique is used on adders, booth multip lie rs and applied for filters to eliminate power consumption due to unwanted data transitions [3]. In [4] they presented a mu ltipliers technique, based on add and shift method and common sub expression elimination for low a rea, low power and high speed imple mentation of FIR filters. Finite impu lse response filters are wide ly used in various DSP applications. Block processing can be applied to digital FIR filters to either increase effective throughput or reduce the power consumption of filter [5]. In [6] they proposed pipelined variable precision gating scheme to reduce power consumption of digital FIR filter. This technique uses clock gating to registers in both data flow direction and vertical to data flow direction. The rest of paper is structured as follows. Section2 gives summary of FIR filter theory, and section3 presents the architectures used in our imple mentation. Section4 gives comparison of imp le menting arch itectures. Section5 provides conclusion of the paper.


    Dig ital filters are very important part of digita l signal processing. Filters have two uses, one is signal separation and other is signal restoration. Signal separation is needed when the signal has been contaminated with noise or other signals. Signal restoration is used when the signal has been distorted in some way. The most common digital filter is linear time invariant filter. In general filtering is described by simp le convolution operation as where is input signal, is convolved output and is filter impulse response.


    Dig ital filters are two types: Finite Impu lse Response (FIR) filters and Infinite Impulse Response (IIR) filters. The filters designed by using finite number of samples of impulse response are called Fin ite Impu lse Response filters. The filters designed by considering all infinite samples of impu lse response are called Infinite Impulse Response Filters. The digital filters are commonly linear t ime invariant filters.

    The straight forward way of imp le menting LTI Fin ite Impulse Response filter is fin ite convolution of input series x[n] with impulse response coeffic ients is given by



    Where is the length of FIR filter, is filters impulse response coefficients, is input sequence and is output of FIR filter. The above equations can also e xpressed in Z domain as


    Where is transfer function of FIR filter in Z do main and is given by



In this paper mu ltiplier and accumulator (MAC) architecture and linear phase folded architecture are considered

    1. MAC Finite Impulse Response filter based on radix4 booth multiplier

      The linear time invariant FIR filter of order L-1 is shown in fig.1. It e mp loys a collection of mult ipliers, adders and tapped delay lines. The weight corresponds to mu ltip lie rs are filter coeffic ients and are referred ass filter coeffic ients. Because of tapped delay line structure, the FIR filter is also called as transversal filter.

      Fig1: Transversal FIR filter

      A mult iplier has two stages. In the first stage, partial products are generated by the encoder and partial product generator (PPG) and are summed by the compressors. In the second stage, the two final products are added to form the fina l product through final adder. The block diagra m of mult iplier is shown in fig.2.

      Fig2: Block diagra m of mu ltip lie r

      The mu ltiplier consists of booth encoder block, compression block, and adder blocks. x and y are input buffers. The multip lie r y is applied to the booth encoder and y is recoded by the booth encoder. x is the mu ltip licand. PPG and compressors are the major part of mu ltip lie r. Ca rry propagation adder adds sum and carry vectors which are coming fro m co mp ressor block. The steps involved in radix4 booth multip licat ion algorith m are described below.

      1. Pad least significant bit of mult iplier with zero.

      2. Pad most significant bit of multip lie r with two zeros (if mult iplier has even number of bits) or with one ze ro (if mult iplier has odd number of bits).

      3. Div ide multip lier in to overlapping groups of three bits.

      4. Determine partia l product scale factor fro m the booth encoding truth table.

      5. Co mpute partial products.

      6. Sum partia l products.

        Table1. Booth encoding truth table

        y y y

        2i+1 2i 2i-1

        Booth op




        0 0 0

        0 0 1

        0 1 0

        0 1 1

        0x 1x 1x 2x






        – 1





        1 0 0

        1 0 1

        1 1 0

        1 1 1










        – 0





        Fro m the above table, booth mult iplier has three operations indicated as direction, shift and addition. Direction indicates whether the mult iplicand is positive or negative. If direction is zero then the mult iplicand will be positive otherwise mu ltiplicand will be negative. Shift indicates whether the multiplication operation involves shifting operation or not. Addition indicates whether the mu ltip licand was added to partial product or not. The e xpressions for these three operations are obtained from the above truth table and are listed below.







        Fig3: Booth encoder and PP where m=2i.

        The booth encoder was constructed by using two xo r gates. Partial product generator was imp le mented using three mult iple xers and an inverter. Carefu l optimization partia l product generation can lead to

        hardware reduction. In the general mult iplication 8*8, eight partial products and seven adders are required. But in the case of booth multip lie r the number of partia l products required for mult iplication is reduced. Hence the number of adders and the power consumption are also reduced.

    2. Linear phase folding architecture FIR filter based on radix4 booth multiplier

      The symmetrica l architecture can be used to imple ment linear phase FIR filter. Because of the symmetrica l a rchitecture the mu ltiplier operations are reduced.

      Fig4: linear phase FIR filter

      Co mparing fig1 and fig 4, the number of mu ltip lie rs reduced half because of the symmetrica l architecture. But nu mber of adders re mains same and the basic model o f this architecture is shown in fig4. For a linear phase FIR filter of o rder N-1,

      where is filter impulse response coeffic ients. The folded architecture provides a trade off between hardware speed the area comple xity. The folding transformation can be used to imp le ment time multip le xed architectures using less area. Because folding transformat ion the power consumption also reduced. The fig.5 shows the linear phase folding architecture.

      Fig5: fold ing architecture of linear phase FIR filte r.

    3. MAC Finite Impulse Response filter relying on serial multiplier and serial adder

      Dig it-seria l imp le mentation styles are best suited for imple mentation of digital signal processing systems. Dig it-seria l mu ltip lie rs are obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence feedback loops . To imple ment multip lier and accumu late FIR, we use low power serial mult ipliers and serial adders. Consider a serial mult iplier shown in fig.6 where the coefficient word length is four b its.

      Fig6: lo w power serial mult iplier

      This architecture consists of four full adders, four mult ipliers and some de lay ele ments. In this mu ltip lie r, the carry out signal of every adder is fed back after a delay to the carry in signal of the same adder. Therefore the crit ical path of this architecture of contains W full adder delays. Where W is the word length. The traditional approach for designing the structure involves unfolding the structure by a factor N. where N is equal to digit size. Which can be further reduced to N full adder delay after pipelining. That reduction is not possible here because of presence of feedback loops.

    4. Finite Impulse Response Filter relaying on shift add multiplier

The shift and add method is used to imple ment FIR filter. In this we perform all our optimization in mu ltip lie r. Here the mu ltiplications are divided into additions and shifts. Hence the comple xity of mu ltip licat ion is reduced.

The coeffic ients in most of digital signal processing applications for the mult iply accu mulate operation are constants. In this method, first we arrange decimal coeffic ients according to positive and negative powers of two. Because of this, the hardware co mple xity of finite impulse response filter and the power consumption will be reduced. The graph form of this method is shown in fig.7. Another form is, coefficients changed to integer by multiply ing the coeffic ients with mu ltip le powers of 10, then arranging the coefficients according positive and negative powers of two.




Fig7: Graph form o f shift add method


Designs equipped to 8 bit adders, 8 bit mu ltip lie rs and are accomplished via VHDL hardwa re description language using Xilin x ISE software and synthesized using Xilin x tools. Powe r is analyzed using Xilin x Xpower analyze r. Tables I and II shows the power consumption comparison of digital FIR filter wh ich uses booth mult iplier, shift add multip lier and serial mu ltip lie r and serial adder.

Table I: power consumption of 8 taps,16 bit coefficients, 8 bit input


Booth without DPDT(mw)

Booth with DPDT using reg(mw)

Booth with

DPDT using and gate(mw)

















Proposed filter














Linear phase

folding booth(mw)





Shift add(mw)





Serial multiplier

ad serial adder





Table II: Power consumption of proposed filters


In this paper a low power and low a rea dig ital FIR filter is presented. For reduce power consumption and area we using radix4 booth multiplier, low powe r serial mu ltip lie r and serial adder, shift add mult iplier and folding transformation. These filte rs are co mpared for power. The proposed FIR filters have been synthesized and imple mented using Xilin x tools and power analyzed using Xilin x Xpowe r analy zer.


T Ra mesh Reddy would like to thank Prof. K. Soundara Rajan, who had been guiding through out to complete the

work successfully, and would also like to thank the HOD, ECE Depart ment and other Professors for extending their help & support in giving technical ideas about the paper and motivating to complete the work e ffective ly & successfully.


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