Implementation of WRVFLN for Testing

DOI : 10.17577/IJERTCONV9IS12046

Download Full-Text PDF Cite this Publication

Text Only Version

Implementation of WRVFLN for Testing

Ashadeepa S N

PG Student Dept. of ECE LAEC Bidar

Basavaling Hiremath

Asst. Professor Dept. of ECE LAEC Bidar

Sadhana C

Professor Dept. of ECE LAEC Bidar

Abstract:- Presently a-days, field programmable entryway cluster (FPGA) is utilized in different space of exploration to plan a PC supported analysis (CAD) framework to group the information continuously. The advantage of utilizing the WRVFLN approach is complex: while ensuring something very similar or higher deformity inclusion of the conventional SBST approach, it decreases the ideal opportunity for test execution, better jelly the processor center Intellectual Property (IP), doesn't need the framework memory to store the test program nor the test information, and can be handily embraced for non-simultaneous on-line testing, since it limits the necessary framework assets. The possibility and viability of the methodology were assessed two or three pipelined processors

Keywords: Hardware, Field programmable gate arrays, Computer architecture, Real-time systems, Very large scale integration


TODAY'S framework on-chip (SoC) climate requires critical changes in testing procedures for memory exhibits. The disappointment of inserted recollections in a SoC is more costly than that of ware recollections on the grounds that a moderately enormous pass on is squandered. Because of the enormous kick the bucket size and the unpredictable manufacture measure for consolidating recollections and rationale, SoCs experience the ill effects of generally lower yield, requiring yield improvement strategies. As of now, the region involved by the inserted recollections takes the greater part of the absolute space of a run of the mill SoC, and the proportion is required to continue to increment later on. The imperfections are along these lines liable to influence the usefulness of the memory clusters as opposed to that of rationale. What's more, the forceful plan rules make the memory clusters inclined to deserts.

Thusly, the generally speaking SoC yield is overwhelmed by the memory yield, and improving the memory yield assumes a significant part in the SoC climate. To work on the yield, memory exhibits are normally outfitted with spare components, and outer analyzers have been utilized to test the memory clusters and design the extra components. Nonetheless, in the SoC climate, the general test time is restrictively expanded if the test reaction information from the memory clusters are shipped off the outside analyzers. Then again, the SoC climate, joined with contracting innovation, permits us more region for on-chip test framework at lower cost than previously, which makes doable an assortment of underlying individual test (BIST) and inherent self-fix (BISR) strategies for decreasing the

test time. Customary equipment individual test (or Built-In Self-Test – BIST) moves the testing task from outside assets (ATE) to interior equipment, blended to create test designs and assess test reactions of the circuit under test. Equipment individual test accomplishes at-speed testing diminishing the general test expenses of the chip.

In this paper, we portray a novel arrangement which blends the Software based individual test SBST and Built-In Self Test BIST standards. The method we propose powers the processor to execute a minimized SBST-like test succession by utilizing an equipment module called Weighted Random Vector Functional Link Network (WRVFLN) unit, which is planned to be associated with the framework transport like a typical memory center, mentioning no adjustment of the processor center inside structure.



Precise Weighted Prediction for Next-Generation Video Coding Standard [1]-In this paper, rakish forecast is used to determine pixel level weight esteems which reuses the rationale in intra expectation to improve on the intricacy. To additionally work on the exactness of expectation, a refinement interaction is presented on the movement vectors utilized for weighted forecast. Test results show that they proposed AWP mode beats the current techniques, and can bring 0.9% bitrate saving in irregular access test and 2.0% bitrate saving in low postpone B test, individually. Weighted forecast assumes a basic part in the video coding techniques yet the customary weighted interaction with fixed weight esteems isn't agreeable for coding of sideways edge areas of two articles. The current strategies burn-through much computational intricacy in pixel-wise weight deduction which need to figure the distance between every pixel position and parcel line.

A 128×128 SRAM Macro with Embedded Matrix-Vector Multiplication Exploiting Passive Gain by means of MOS Capacitor for Machine Learning Application [2]-In- memory figuring (IMC) has arisen as an alluring option in contrast to ordinary advanced execution of AI calculation, since it can accomplish high energy proficiency by restricting the information development among memory and preparing unit. In earlier IMC works, multi-bit input is encoded into either beat tally or heartbeat width or a simple voltage utilizing a DAC which drives the read cycle line (RBL) or read word-line (RWL) port of the bit cell. Such current-space calculation experiences static force devoured

by the DAC and is restricted by the linearity of the current sources requiring adjustment. In correlation, charge-area calculation loosens up the linearity, and static force utilization issue; notwithstanding, earlier work has just investigated restricted boundary accuracy, for example BNN, and is liable to flag lessening because of charge misfortune over parasitic components. Besides, those earlier expressions need backing of either bad information or negative/zero loads, keeping from executing a more extensive scope of organizations in the IMC equipment.

Copula-Based Reliability for Weighted-k-Out-of-n Systems Having Randomly Chosen Components of m Different Types[3]-In this article, they think about a weighted-k – out-of-n framework having m2 kind of segments each with its own positive whole number esteemed weight, in which the arbitrary lifetimes of parts are reliant. This framework should work with execution level k if and just if the absolute load of working parts of numerous types is basically k . The construction of reliance of the framework part lifetimes is displayed by the copula work. Additionally, it is expected that the arbitrary numbers Ni of segments are looked over class Di for type I . The unwavering quality of the framework is acquired as a combination of the dependability of weighted-k – out-of-n frameworks comprising of m sorts of segments with fixed number of them as far as the likelihood mass capacity of the arbitrary vector (N1, ,Nm1) . Then, at that point, a copula-based articulation for part significance in each class is acquired, and illustrative models are introduced.

A Multi-Kernel Mode Using a Local Binary Pattern and Random Patch Convolution for Hyperspectral Image Classification[4]-This article proposes a multikernel strategy dependent on a neighborhood paired example and arbitrary patches (LBPRP-MK), which incorporates a nearby parallel example (LBP) and profound learning into a numerous piece structure. To start with, they use LBP and various leveled convolutional neural organizations to extricate neighborhood textural highlights and multi-facet convolutional highlights, individually. The convolution portion for the convolution activity is gotten from the first picture utilizing an arbitrary technique without preparing. Then, at that point, they inut neighborhood textural highlights, multi-facet convolutional highlights, and unearthly highlights got from the first picture into the spiral premise capacity to get three portion capacities. At last, the three piece capacities are converged into a multikernel work as per their ideal loads under the composite part technique. This multikernel work is utilized as the contribution for the help vector machine to get the characterization result map. Examinations show that contrasted and other HSI grouping strategies, they proposed technique accomplishes better order execution on three HSI datasets With the advancement of profound learning innovation, an ever increasing number of researchers have applied it to hyperspectral picture (HSI) characterization to further develop arrangement exactness. Nonetheless, these profound learning techniques not just take a great deal of time in the pre-preparing stage, yet in

addition have somewhat restricted grouping execution when there are less named tests. To further develop order execution while lessening costs

A productive Robust Random Vector Functional Link network for Solar Irradiance, Power and Wind speed prediction[5]-This in this paper proposes a proficient strategy for expectation of sun oriented irradiance, sunlight based force and wind speed at various time spans (for example 5min, 10min and 60min). With the consideration of chronicled sunlight based irradiance, force and wind speed information, a super short Prediction model has been set up which is known as Robust Regularized Random Vector Functional connection (RRVFL) organization. This technique uses a weighted factor in edge regularized model, for preparing the examples to survey the loads in yield layer. A Huber's expense work has been applied to acquire the power here. To get the exactness of they proposed approach, the test has been done with sunlight based and wind for different time stretches in various barometrical condition. The outcome shows that they proposed RRVFL strategy is predominant as contrasted and different models (for example Arbitrary vector practical connection (RVFL) and Robust Extreme learning machine(R-ELM), and so forth Sun powered and wind information of California, USA has been taken here. They proposed model can be approved progressively situation by utilizing test seat application and in enterprises of sun powered and wind ranch

A Weighted-Sample-Based Random Vector Generation calculation for resampling[6]-In this paper , which avoids the assessment of the obscure thickness and requires not many presumptions on the covered appropriation. Consequently, this strategy is especially reasonable for arbitrary vector age, and can be utilized for resampling in Particle Filter (PF) when the overall Gaussian presumption decays. Its legitimacy and exhibitions are checked in the recreations, where they proposed calculation is contrasted and regularization, for approximating a Gaussian blend model and resampling in a non-direct following. Arbitrary number age is the piece of Monte Carlo strategy and reenactment, and it's occasionally important to produce an irregular vector from an obscure appropriation portrayed by a gathering of weighted examples. In view of the possibility of fractional estimation, a novel Weighted- Sample-Based Random Vector Generation (WSB-RVG) calculation is proposed


    Fig 1 shows the fundamental design of a PRESTO generator. A n-bit PRPG associated with a stage shifter taking care of sweep chains shapes a portion of the generator delivering the genuine pseudorandom test designs. A straight input shift register or a ring generator can carry out a PRPG. The n hold hooks are set between the PRPG and the stage shifter. Each hold hook is separately controlled through a relating phase of a n-bit switch control register. As long its empower input is declared, the given hook is straightforward for information

    going from the PRPG to the stage shifter, and it is supposed to be in the switch mode. At the point when the hook is impaired, it catches and saves, for various clock cycles, the relating piece of PRPG, subsequently taking care of the stage shifter with a steady worth. It is presently in the hold mode. It is significant that each stage shifter yield is acquired by XOR-ing yields of three distinctive hold locks. Accordingly, every sweep chain stays in a low-power mode gave just impaired hold locks drive the relating stage shifter yield.

    Fig.1 Basic architecture of a PRESTO generator.

    The switch control register administers the hold locks. Its substance includes 0s and 1s, where 1s show hooks in the switch mode, in this manner straightforward for information showing up from the PRPG. Their part decides a sweep exchanging action. The control register is reloaded once per design with the substance of an extra shift register. The empower signals infused into the shift register are delivered in a probabilistic design by utilizing the first PRPG with a programmable arrangement of weights.The loads are dictated by four AND entryways creating 1s with the likelihood of 0.5, 0.25, 0.125, and 0.0625, separately. The OR entryway permits picking probabilities past basic forces of 2. A 4-cycle register Switching is utilized to initiate AND doors, and permits choosing a client characterized level of exchanging movement. For instance, the exchanging code 0100 will set to 1, all things considered, 25% of the control register stages, and accordingly 25% of hold locks will be empowered. Given the stage shifter structure, one can evaluate then the measure of output chains getting steady qualities, and accordingly the normal flipping proportion. An extra 4- input NOR door identifies the exchanging code 0000, which is utilized to turn the LP usefulness off. It is significant that when working in the weighted irregular mode, the exchanging level selector guarantees measurably stable substance of the control register as far as the measure of 1s it conveys. Accordingly, generally similar part of sweep chains will remain in the LP mode, however a bunch of real low flipping chains will continue to change starting with one test design then onto the next. It will compare to a specific degree of flipping in the sweep chains.


    Ring generators are the better LFSR which produces pseudo arbitrary test designs which produces double groupings. Two adjoining flip-flop contains all things considered one 2 information XOR entryway and each flip- flop yield drives all things considered 2 fan out hubs. The circuit is developed in ring structure so there is no long input way interfacing the right flip-lemon to one side most flip-flop.

    Fig 2 Proposed System

    The center guideline of the decompressor is to debilitate both weighted rationale blocks (V and H) and to convey deterministic control information all things considered. Specifically, the substance of the switch control register would now be able to be chosen in a deterministic way because of a multiplexer set before the shift register. Besides, the Toggle and Hold registers are utilized to on the other hand preset a 4-digit double down counter, and along these lines to decide spans of the hold and switch stages. At the point when this circuit arrives at the worth of nothing, it makes a devoted sign go high to flip the T flip- flop. A similar sign permits the counter to have the information kept in the Toggle or Hold register entered as the following state. Both the down counter and the T flip- flop should be instated each test design.

    The underlying worth of the T flip-flop chooses whether the decompressor will start to work either in the switch or in the hold mode, while the underlying worth of the counter, further alluded to as a counterbalance, and discovers that mode's term. The usefulness of the T goes back and forth stays as before as that of the LP PRPG however two cases. As a matter of first importance, the encoding strategy may totally impair the hold stage (when all hold hooks are obstructed) by stacking the Hold register with a fitting code, for instance, 0000. Whenever distinguished (No Hold signal in the figure), it abrogates the yield of the T flip-flop by utilizing an extra OR

    entryway, as displayed in Fig 4.1. Therefore, the whole test design will be encoded inside the switch mode solely. What's more, all hold hooks must be appropriately introduced. Henceforth, a control signal First cycle created toward the finish of the ring generator introduction stage reloads all hooks with the current substance of this piece of the decompressor

    BIST is a plan for-testability strategy that puts the testing capacities genuinely with the circuit under test (CUT), as shown in Fig 1. The fundamental BIST engineering requires the expansion of three equipment squares to an advanced circuit: a test design generator, a reaction analyzer, and a test regulator. The test design generator produces the test designs for the CUT. Instances of example generators are a ROM with put away examples, a counter, and a direct input shift register (LFSR). A common reaction analyzer is a comparator with put away reactions or a LFSR utilized as a mark analyzer. It compacts and examines the test reactions to decide rightness of the CUT. A test control block is important to enact the test and break down the reactions. In any case, as a rule, a few test-related capacities can be executed through a test regulator circuit.


    Fig. 3 Flow diagram of WRVFLN classifier implementation in hardware for the classification of data.

    Fig. 3 presented the flow diagram of WRVFLN classifier implementation in hardware for classification of data

    Fig. 4. Weighted Random vector functional link neural network digital architecture implementation in hardware platform

    The advanced design of WRVFLN classifier as displayed in Fig. 2. To address a mathematical amount, we have considered sign two's supplement fixed-point portrayal with 16 pieces, where whole number worth is addressed by 3 pieces, decimal worth is addressed by 12 pieces with a sign piece. In this article, the diabetes testing dataset is taken for equipment execution reason. At first all the element vectors of diabetes dataset are put away in 8 square arbitrary access memory (BRAM) as dataset contains 8 highlights. To handle the information, we have utilized 8- digit input-select line because of 2 8 = 256, all the BRAMs produce the yield at a time according to enter select line esteem. The secret layer arbitrary weight (w) is addressed by 0, ± 1 2 , ± 1 4 , ± 1 8 and so forth are put away in barrel shifter. 8 BRAMs produce 8 yields all at once and took care of into 18 barrel shifters as 18 secret hubs are consider for this investigation. Every multiplexer has 18 sources of info and one yield, 8 multiplexers are utilized to handle 8 highlights, the yield of multiplexers are prepared through modifying unit to address the indication of covered up layer irregular loads. Snake unit produces Pp i=1 wi ·Ii without predisposition to stay away from equipment execution intricacy. In this paper to decrease the computational intricacy, right barrel shifter is utilized to delivered increase result without multiplier. Multiquadratic enactment work is applied on viper yield to extricate the secret layer yield H (I).


    The WRVFLN unit works like a memory center, taking care of the processor with values relating to get together directions, in this manner empowering the execution of projects. A multiplexer grants to drive the information transport with directions coming either from the code memory (when in typical mode) or from the WRVFLN unit (when in test mode). This diagram is like a typical memory BIST situation.

    Fig. 5. Schematic view of the WRVFLN unit architecture

    Fig. 5 shows theWRVFLNunit engineering. Address, Control and Data transports are perused by the WRVFLN

    unit both to screen them (to recognize potential flaws) and to conform tothe transport convention when it should compose on them.

    The design of the WRVFLN unit incorporates:

    • An guidance register, holding the worth to be put on the transport when the CPU plays out a read cycle.

    • A set of inward recollections for putting away the encoded data about the guidelines to be created, falling back on an impromptu guidance set including:

      • PCode words, distinguishing guidelines and including data about their execution under the WRVFLN unit control;

      • OPErand words, depicting operands to be applied and their development along the program.

        With the end goal of this task we expect that either the processor center doesn't utilize any store, or they are crippled during test. In a framework including a WRVFLN unit, when in test mode, the framework recollections are not, at this point got to. Every one of the gets, peruse and compose tasks are performed straightforwardly with the WRVFLN unit, and the unit acts towards the processor as though it's anything but a store. Subsequently, the test performed utilizing the WRVFLN approach has a similar presentation we could accomplish bringing the test program from the guidance store. When in test mode, the WRVFLN unit replaces the code memory, and interfaces with the processor over and again playing out the accompanying activities:

        • Detects a guidance bring cycle

        • Reads and deciphers directions from its memory

        • Generates a guidance code for the processor

        • Observes the processor conduct by compacting the qualities going on the location, information and control transports.

        The inward recollections can be executed in RAM and the encoded test program stacked utilizing the TAM, or they can be carried out with non-unstable components, for this situation the encoded test projects will be designed inside the WRVFLN module. Such a methodology is savvy for on-line test application.

        Two guidance age modules, to be specific:

    • The opcode Generation (OPCG) module: responsible for creating chip guidance opcodes;

    • The operand Generation (OPEG) module: responsible for creating guidance operands. It very well might be reproduced more than once, contingent upon the ISA of the processor under test (i.e., on the most extreme number of operands of a guidance); this module executes the straightforward controls that might be applied to an operand inside a circle, like shift, increase, and so forth

      AControl Unit, dealing with the general application stream in a joint effort with the Bus Interface Unit.

      A Bus Interface Unit, perusing and composing the framework transport.

      A Results Collection module, packing the checked location, information and control transport signals, is responsible for creating the test signature. This capacity is appropriate to be executed by a MISR module.

      An discretionary Test Access Mechanism module, responsible for interfacing the WRVFLN unit with the Automatic Test Equipment in the event that the encoded guidance arrangement must be transferred from an external perspective. The IEEE 1149.1 test access port (TAP) can be utilized for this reason. In any case, this module isn't obligatory and doesn't exist if the test program is designed in the WRVFLN unit, as it is possible when managing on- line test.

      Fig. 6 WRVFLN Instruction Set Architecture

      The format used to store each compressed instruction in the WRVFLN internal memories is shown in Fig. 6.

      The OPCode word includes the following fields:

    • opcode: contains a bit string identifying an instruction to be written on the system bus; since the opcode length may differ from instruction to instruction, the opcode field accounts for a number of bits sufficient to contain the largest instruction opcode

    • length: it is a companion of the opcode field and indicates how many bits the instruction counts.

    • iloop: this field states whether the instruction is part of a loop (called inner loop) the most significant bit (MSB) is set to 1 to identify the starting and the ending instructions in the loop the other bits indicate how many iterations have to be executed in the inner loop; in case the MSB is set to 0 and other bits differ from 0, a single instruction inner loop is encountered.

    • nop: it is used to signal that the instruction has to befollowed by a sequence of NOP instructions.The OPErand word includes the following fields:

    • operand seed: it contains the seed to be utilized to begin the parametric operand arrangement in the encoded program rendition.

    • repetition: it is a discretionary field demonstrating whether the seed must be reproduced to fit the operand length; this is helpful if there should arise an occurrence of customary information to save space.

    • manip: each cycle in this field compares to an




      intelligent or number-crunching administrator to be applied to the operand seed, e.g., left-shift (<< ) and increase (+1 ).Abit set to 1 implies that the relating administrator is applied; administrators are applied all together, beginning from the main piece in the field.

      Previous work

      Proposed work


      On the off chance that each piece is set to 0 the operand remains fix.

    • rst: if there should be an occurrence of directions included into inward circles, it shows whether the first seed must be reestablished when returning the main cycleTo complete the encoded program description, a shadow register is also stored within the Control Unit:

    • oloop: a register that indicates how many complete iterations have to be performed (outer loop).

  5. COMPARISON ANALYSIS Comparison table is based on the convolution-based

    designs and with respect to our designTable 1: Convolution versus Proposed scheme

    Convolution Scheme

    Proposed Scheme

    Require more number of multiplication

    Less number of multiplication

    More number of addition

    Less number of addition

    Require more memory

    Less memory

    Require large area

    Small area required

    Time consumption more

    Time consumption less

    Table 2: Comparison of parameters


    Previous Work Overview

    Proposed work overview

    WRVFLN Scheme






    Shifting Method


    No ( Not Required for Parallel Bit)

    Frame Memory


    No ( Not Required for Parallel Processing)

    Hardware Implementation




    Previous work

    Proposed work




    Table 3: Power analysis with previous and proposed work

    Figure 7 Overview of power

    Table 4 Area analysis with previous and proposed work

    Parameter s

    Previous work/Numbe r of slices

    Proposed work/Number of slices


















    Previous work/Number of slices

    Proposed work/Number of slices

    Previous work/Number of slices

    Proposed work/Number of slices

    Figure 2 Overview of Area


The expense for applying the new technique is restricted to the inclusion of the WRVFLN unit (with no adjustment of the processor center); exploratory outcomes we accumulated on two experiments dependent on the miniMIPS and OpenRISC processors show that this unit has a somewhat decreased size. Further trial results exhibit that the technique permits accomplishing a similar issue inclusion of the SBST approach with diminished test time and much lower prerequisites as far as use of the framework memory. We are at present working is going on towards creating WRVFLN units ready to help the selection of the technique to a more extensive number of processors.


[1]. YuchengSun;FangdongChen;LiWang;ShiliangPuAngular Weighted Prediction for Next-Generation Video Coding Standard 2021 IEEE International Conference on Multimedia and Expo (ICME) Year: 2021 | Conference paper | Publisher: IEEE

[2]. Rezwan A Rasul;MikeShuo-Wei Chen A 128×128 SRAM Macro with Embedded Matrix-Vector Multiplication Exploiting Passive Gain via MOS Capacitor for Machine Learning Application 2021 IEEE Custom Integrated Circuits Conference (CICC) Year: 2021 | Conference Paper | Publisher: IEEE

[3]. EisaMahmoudi;Rahmat Sadat Meshkat;HamzehTorabiCopula- Based Reliability for Weighted-k-Out-of-n Systems Having Randomly Chosen Components of m Different Types IEEE Transactions on Reliability Year: 2021 | Early Access Article | Publisher: IEEE

[4]. Wei Huang;YaoHuang;ZebinWu;JunruYin;Qiqiang Chen A Multi- Kernel Mode Using a Local Binary Pattern and Random Patch Convolution for Hyperspectral Image Classification IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing Year: 2021 | Volume: 14 | Journal Article | Publisher: IEEE

[5]. S P Mishra;PriyankaPriyadarshiniPadhi;JyotirmayeeNaik;P. K. Dash;LokanathTripathy;Naeem M.S. Hannoon;R. Senapati An efficient Robust Random Vector Functional Link network for Solar Irradiance, Power and Wind speed prediction 2021 1st Odisha International Conference on Electrical Power Engineering, Communication and Computing Technology(ODICON) Year: 2021 | Conference Paper | Publisher: IEEE

[6]. FeitengLuo;DongjinWang;Weidong Chen A Weighted-Sample- Based Random Vector Generation algorithm for resampling 2010 International Conference on Image Analysis and Signal Processing Year: 2010 | Conference Paper | Publisher: IEEE

[7]. Yu Liu;YilinWu;Wenzhao Pan Dynamic RGB-D SLAM Based on Static Probability and Observation Number IEEE Transactions on Instrumentation and Measurement Year: 2021 | Early Access Article | Publisher: IEEE

[8]. Goncalves Martins, V.M. Low cost fault detector guided by permanent faults at the end of FPGAs life cycle Test Workshop –

LATW, 2014 15th Latin American 12-15 March 2014

[9]. Dogaru, E. ; A flexible BIST strategy for SDR transmitters Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 24-28 March 2014

[10]. Zhenqian Zhang Face-to-face bus design with built-in self-test in 3D ICs 3D Systems Integration Conference (3DIC), 2013 IEEE International 2-4 Oct. 2013

[11]. Valfre, J. ; Syst. Test Directorate, Raytheon Missile Syst., Tucson, AZ, USA Testability modeling usage in design-for-test and product lifecycle cost reduction AUTOTESTCON, 2012 IEEE 10- 13 Sept. 2012

[12]. Bernardi, P. ;Dipt. di Autom. e Inf., Politec. di Torino, Torino, Italy ; Ciganda, L. ; De Carvalho, M. ; Grosso, M. On-line software- based self-test of the Address Calculation Unit in RISC processors Test Symposium (ETS), 2012 17th IEEE European 28- 31 May 2012

[13]. Huang Shaofeng Online condition monitoring methodology for relay protection based on self-test information Advanced Power System Automation and Protection (APAP), 2011 International Conference on 16-20 Oct. 2011

[14]. Das, N. ; Sch. of VLSI Technol., Bengal Eng. & Sci. Univ., Shibpur, India ; Roy, P. ; Rahaman, H. ; Dasgupta, P. Build-in-Self-Test of FPGA for diagnosis of delay fault Quality Electronic Design (SQED), 2011 3rd Asia Symposium on 19-20 July 2011

[15]. Foutris, N. ; MT-SBST: Self-test optimization in multithreaded multicore architectures Test Conference (ITC), 2010 IEEE International 2-4 Nov. 2010

[16]. Baojiang Sun ; An Automatic Design Technique for Hardware System of ATS Autotestcon, 2006 IEEE 18-21 Sept. 2006

Leave a Reply