 Open Access
 Total Downloads : 298
 Authors : Mageshwar. S, Saranya. P
 Paper ID : IJERTV3IS20511
 Volume & Issue : Volume 03, Issue 02 (February 2014)
 Published (First Online): 24022014
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Implementation of Binary Image Processing with Morphology Operation
Mageshwar. S1, Saranya. P2
1PG Scholar, Sriguru Institute of Technology, Coimbatore641 110, India
2Assistant Professor, ECE, Sriguru Institute of Technology, Coimbatore641 110, India
Abstract Binary image processing is a powerful tool in many image and video processing applications, target tracking, multimedia application, and computer vision. Binary image processing chips have been designed to generalize the binary image applications of a chip. Chips were presented to progress basic binary morphological operations such as dilation, erosion, opening and closing. The processors architecture is consists of a combination of reconfigurable binary processing module, input and output image control units. The reconfigurable binary processing module, which consists of fine and mixedgrained reconfigurable binary compute units and output control logic, works binary image processing operation especially mathematical morphology operations and implements related motion detection algorithms more than 237 frames per second for any image. The simulation and experimental results is suitable for realtime binary image processing applications.
KeywordsBinary Image processor, fieldprogrammable gate array (FPGA), mathematical morphology operation, mixed grained, median filter.

INTRODUCTION
Binary image processing is a powerful tools and extremely used in different areas, such as object recognition, tracking, motion detection and machine intelligence [1][7], image analysis [8], video processing [10], computer vision, and identification & authentication systems [13][16]. Binary image processing has been commonly implemented using processors such as CPU or DSP.
Highspeed implementation of binary image processing operations can be efficiently realized by using specialized chips for binary image processing. Therefore, binary image processing module chips have attracted much more attention in the field of image processing. The major drawback of applicationspecific chips is the lack of flexibility. The reconfigurable processing technique can bridge the gap between applicationspecific integrated circuits and flexibility.
A reconfigurable binary image processing system with high flexibility, performance, small size, and low power consumption can be implement in a single chip. Most reconfigurable vision chips can realize a reconfigurable computing by processing an element array [11], [12]. A reconfigurable image processing accelerator incorporating eight macro processing elements was designed to support real time change detection and background registration based on video and object segmentation algorithm. Nowadays, a vision chip with the architecture of a massively parallel cellular array of processing elements was presented for image processing by using the asynchronous or synchronous processing technique
[12]. It has been a common practice to build application specific chips for realtime binary image processing [20]. Other generalpurpose chips have the architecture of a digital processor array in which each digital processor handles one pixel.When large sized images are processed, the chips will become extremely large. Further, these are needed to design a high performance, small size, and large application range chip for realtime binary image processing .This paper presents a binary image processor that consists of a reconfigurable binary processing module, including reconfigurable binary compute units and output control logic, input and output image control unit circuits. The processor is implemented to perform real time binary image processing. It is found that the processor can process pixellevel images and extract image features, such as boundary and motion detection of images. The processor has the advantages of high speed, simple structure, and various application ranges.

RELATED WORKS

Image analysis
Its only a slight oversimplification to say that the fundamental problem of image analysis is pattern recognition the purpose of which is to recognize image patterns corresponding to physical objects in the scene and determine their pose (position, orientation, size, etc.) [9]. Often the results of pattern recognition are all thats needed, for example a robot guidance system supplies an objects pose to a robot, and in other cases a pattern recognition step is needed to find an object so that it can be inspected for defects or correct assembly.

Pixel Mapping
Point transforms include a large set of enhancements that are useful with scalarvalued pixels (e.g. monochrome images). Often these are implemented by a single software routine (or hardware module) that uses a lookup table. Lookup tables are fast and can be programmed for any function offering the ultimate in generality at reasonable speed. Pixel maps are most useful when the function is computed based on global statistics of the image. One can process an image to have a desired gain and offset, for example, based on the mean and standard deviation, or alternatively, the minimum and maximum, of the input.

Noise Reduction Filtering
Noise reduction is the process of removing noise from a signal. All recording devices, both analog or digital have traits which make them susceptible to noise. Noise can be random or
white noise with no coherence, or coherent noise introduced by the device's mechanism or processing algorithms.
In the case of photographic film and magnetic tape, noise (both visible and audible) is introduced due to the grain structure of the medium. In photographic film, the size of the grains in the film determines the film's sensitivity, more sensitive film having larger sized grains. In magnetic tape, the larger the grains of the magnetic particles (usually ferric oxide or magnetite), the more prone the medium is to noise.


MORPHOLOGY OPERATIONS

Dilation
Gradually enlarges the boundaries of regions of foreground pixels (i.e. white pixels, typically). Areas of foreground pixels grow in size while holes within those regions become smaller. Input to dilation operator: Image and structuring element [1], [3].
In other words, for each background (input) pixel, superimpose the structuring element with the input image. If at least one pixel in the structuring element coincides with a foreground pixel in the image underneath, then the input pixel is set to the foreground value. If all the corresponding pixels in the image are background however, the input pixel is left at the background value.
Figure1. Dilation
The dilation of A by the structuring element B is defined by:
Example application: Dilation is the dual operation of the erosion. Figures that are very lightly drawn get thick when "dilated". Easiest way to describe it is to imagine the same fax/text is written with a thicker pen.

Erosion
The basic effect of the operator on a binary image is to erode away the boundaries of regions of foreground pixels (i.e. white pixels, typically). Shrink areas of foreground pixels in size and holes within those areas become larger.
In other words, For each foreground (input) pixel, superimpose the structuring element with the input image. The input pixel is left as it is if it is the foreground pixel in the structuring element. If any of the corresponding pixels in the image are background however, the input pixel is also set to background value.
Figure2. Erosion
The erosion of the binay image A by the structuring element B is defined by:
,
Where Bz is the translation of B by the vector z,
,.
The dilation is commutative, also given by:
If B has a center on the origin, as before, then the dilation of A by B can be understood as the locus of the points covered by B when the center of B moves inside A. In the above example, the dilation of the square of side 10 by the disk of radius 2 is a square of side 14, with rounded corners, centered at the origin. The radius of the rounded corners is 2.
The dilation can also be obtained by:
Where Bs denotes the symmetric of B, that is,
When the structuring element B has a center (e.g., B is a disk or a square), and this center is located on the origin of E, then the erosion of A by B can be understood as the locus of points reached by the center of B when B moves inside A. For example, the erosion of a square of side 10, centered at the origin, by a disc of radius 2, also centered at the origin, is a square of side 6 centered at the origin. The erosion of A by B is also given by the expression:
Example application: Assume we have received a fax of a dark photocopy. Everything looks like it was written with a pen that is bleeding. Erosion process will allow thicker lines to get skinny and detect the hole inside the letter "o".

Opening
An Erosion followed by a dilation using the same structuring element for both operations.
Inputs: Image for opening and structuring element somewhat like erosion it tends to remove some of the foreground (bright) pixels from the edges of object region and used to
preserve foreground regions that have a similar shape to the structuring element.
Grey level opening consists simply of greylevel erosion followed by greylevel dilation. The opening of A by B is obtained by the erosion of A by B, followed by dilation of the resulting image by B:
Figure 3 Opening.
The opening is also given by
In which means that it is the locus of translations of the structuring element B inside the image A. In the case of the square of side 10, and a disc of radius 2 as the structuring element, the opening is a square of side 10 with rounded corners, where the corner radius is 2.
Example application: Let's assume someone has written a note on a nonsoaking paper and that the writing looks as if it is growing tiny hairy roots all over. Opening essentially removes the outer tiny "hairline" leaks and restores the text. The side effect is that it rounds off things. The sharp edges start to disappear.

Closing
Its a dilation followed by erosion using the same structuring element for both operations. Enlarges the boundaries of foreground (bright) regions in an image Shrinks background color holes and Less destructive of the original boundary shape.
Operation determined by a structuring element. Preserves background regions that have a similar shape to the structuring element
Figure 4 Closing.
The closing of A by B is obtained by the dilation of A by B, followed by erosion of the resulting structure by B:
.
The closing can also be obtained by
In where Xc denotes the complement of X relative to E (that is,
).
The above means that the closing is the complement of the locus of translations of the symmetric of the structuring element outside the image A.


DESIGN AND IMPLEMENTATION

Design Criteria
Reconfigurable binary image processing chips have been designed to generalize the binary image applications of a chip. Chips were presented to perform basic binary morphological operations, such as dilation, erosion, opening, and closing. Programmable analog vision processors based on the cellular neural or nonlinear network universal machine architecture were proposed for a wide range of applications such as motion analysis and texture classification. A programmable single instruction multiple data (SIMD) real time vision chip was presented to achieve highspeed target tracking.

Block Diagram
A reconfigurable image processing accelerator incorporating eight macroprocessing elements was designed to support realtime change detection and background registration based on video object segmentation algorithm. Recently, a vision chip with the architecture of a massively parallel cellular array of processing elements was presented for image processing by using the asynchronous or synchronous processing technique.
Reconfigurable binary processor module
Input control logic unit
Binary image processor Input signal
Output control logic
Figure5 Block diagram of binary image processor
The presented processor is designed for applications in image or video processing, computer vision, machine intelligence, and identification and authentication systems. Such systems should have a high flexibility and high performance processor for wide applications; therefore, the processor design is focused on high flexibility and speed. Some of the conventional works are designed for specific applications and some have large areas and high power consumption. Then, a reconfigurable binary processing module with high speed and simple structure is implemented for wide use and consuming fewer hardware resources.
Figure6 Block Diagram of the reconfigurable binary processing module.
It can be divided into two main parts. The first part is the output control logic, which selects the output from all the binary compute unit outputs according to the given parameters and converts the series data of 1b binary images into parallel data. The second part consists of several binary compute units that perform binary logic and binary image operations at a high speed. The binary image algorithms are realized by the operations in the individual binary compute units and the connection pattern of these units. The units can execute binary image operations in a pipelined or parallel manner. The operation executed in a binary compute unit is decided by configurable registers, including logic operation parameters, image resolution parameters; mask sizes, input and output selection parameters, and auxiliary parameters.

Binary Compute Unit
The architecture of the binary compute unit which has two binary compute elements and one set of operation elements can perform logic, reduction, median filtering and set operations. The binary compute unit has a mixedgrained architecture that has high flexibility,
Figure7. Block Diagram of Binary Compute Unit.
Efficiency and performance. Granularity refers to the level of data manipulation. Usually, two types of granularity are distinguished: finegrained, which corresponds to the bitlevel manipulation of data and coarsegrained, which corresponds to the word level. The finegrained architecture is highly flexible and the coarsegrained architecture has fewer reconfiguration parameters and is highly efficient.
The set operation element can perform binary set operations, such as union, intersection, complement, subtraction, addition, and straightthrough output. The inputs of the set operation element and the outputs of the binary compute unit are transmitted via two sets of multiplexers, respectively, which makes the unit architecture more flexible. The inputs transmitted to the set operation element via the multiplexers can be the operation results of the binary logic elements, the reduction result, and the median filtering result. The outputs of the binary compute unit transmitted via multiplexers can be the original input of the binary compute unit, the operation results of the binary logic elements, the
reduction result, the median filtering result, and the operation result of the set operation element. The set element has a fine grained architecture. The operands of the set element are 1 b; therefore, the set element has a 1b logic block and shows high flexibility and efficiency.

Binary Compute Element
The binary compute element comprises two input control multiplexers, n binary logic elements, a binary reduction element, and a binary median filter. The input control multiplexer selects input data for the binary logic element from the line memories, the SDRAM, and the parameters in the register group. When a video image is processed, line memories are needed to buffer image signals before they are input to binary logic elements. When the block size of the image to be processed is n Ã— n, n 1 line memories with a depth equal to the image width are needed to buffer the image signals. When images other than videos are processed, the input data are selected from the parameters in the register group or SDRAM. The binary logic element can perform operations such as AND, OR, NOT, NAND, NOR, XOR, XNOR, and straightthrough output.
Figure8. Block Diagram of Binary Compute Element.
The reduction element performs operations such as reduction AND, reduction OR, reduction NAND, reduction NOR, reduction XOR, reduction XNOR, and straight through output. The set element performs operations such as union, intersection,
complement, subtraction, and XOR. All the operation results from the binary logic elements, the reduction element, and the binary median filter are synchronized and output via multiplexers to the next binary compute unit. The binary compute element has a coarsegrained architecture featured by high performance and short reconfigurable time. The binary compute unit has the characteristic of programmability and configurability since the programmable logic is applied in the design of the binary logic element, reduction element and binary median filter in the binary compute element, the set element, and the multiplexers. In sum, the binary compute unit is appropriate for binary image processing due to its high performance, flexibility, and short configuration time.


RESULTS AND DISCUSSIONS
As per the reconfigurable binary image processing architecure,the image is initallypassed through the input control logic unit. It can performthe some binary set of operation such as union, intersection, complement, substract, addition and straight through output. Where the blurring effects, salt and pepper noise are removed afterthat rank
order filter is performed on the filtered output to obtain a scaled image.
Figure9 Results for binary compute unit.
Above the figure shows result of binary compute unit. Binary compute unit performs binary set of operation element and binary compute element. Input image passed through the binary compute element and to perform the binary set of operation such as union, intersection, complement and addition. Binary compute element provides the output of median filter, reduction filter and logic outputs are passed through the binary compute unit via MUX. The binary compute unit can used to reduce size of the image and noise.

CONCLUSION
Hence a novel reconfigurable binary image processor technique is presented to develop a lowcost, lowpower, low memory requirement, high flexibility and high performance for realtime applications. A vision system with high flexibility and performance, small size and low power consumption can be implemented in a single chip. When compared with the digital part, the analog part shows low robustness, accuracy and scalability although it has a small area and low power consumption. The dynamic reconfiguration approach was used to increase the processor performance. Basic mathematical morphology operations and complicated algorithms can easily be implemented on it because of its simple structure. Most reconfigurable vision chips realize reconfigurable computing by processing an element array. They can be used in image or video processing, target tracking, multimedia applications, and computer vision
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