FPGA-Based Implementation of A TMR and CRC Enabled Fault-Tolerant Data Transmission System

FPGA-Based Implementation of A TMR and CRC Enabled Fault-Tolerant Data Transmission System

M. Pandimeena

Assistant Professor, Department of ECE, Sri Bharathi Engineering College for Women, Pudukkottai, India.

Abstract – In safety-critical industries like aerospace, healthcare, and telecommunications, reliable data transmission is essential. This paper suggests a fault- tolerant design that combines Triple Modular Redundancy (TMR) and Cyclic Redundancy Check (CRC-16) to improve error detection and correction. TMR replicates data across three independent modules, using majority voting to mitigate single-point failures, while CRC-16 provides effective detection of single-bit and burst errors during transmission. The architecture is implemented using Verilog HDL. Simulation results validate the design's resilience, low latency, and high throughput.

Key Words: Fault-Tolerant Data Transmission, Triple Modular Redundancy (TMR), Cyclic Redundancy Check (CRC), VLSI, Error Detection and Correction, Majority Voting Logic, Verilog HDL, Fault Injection, Hardware Redundancy.

1. INTRODUCTION

   This paper describes a fault-tolerant data transmission system designed to guarantee consistent data correctness, which is vital in mission-critical industries such as aerospace, healthcare, and industrial automation. The suggested system combines Triple Modular Redundancy (TMR) to mask faults and Cyclic Redundancy Check (CRC) to detect transmission problems, resulting in a robust and resilient architecture capable of handling single-fault scenarios. By combining TMR's duplicated modules with CRC's robust error-checking capability, the system achieves excellent reliability with minimum performance overhead.

   The design uses CRC-16 encoding and decoding for error detection, as well as majority voting within the TMR framework for data recovery in case of differences. The system was created with Verilog HDL and validated by simulations, including fault injection scenarios. The system successfully detects and corrects transmission faults while maintaining high throughput and low latency.This fault- tolerant system is scalable and adaptable for high-reliability situations, preserving data integrity despite hardware or communication problems.The proposed methodology addresses the demand for reliable data transmission methods in safety-critical systems.

2. RELATED WORKS

   This study [1], Fault tolerance in IoT systems is examined in this study, with a focus on its significance across several architectural layers (e.g., network, sensing, computing). In order to increase system availability and dependability, it examines methods (replication, network control), architectural patterns (centralized, hybrid), and styles (microservices, publish-subscribe). Additionally, the report discusses future research directions and current trends for improving IoT fault tolerance.

   In this paper [2], In this system tracks water levels with sensors and transmits live data to a cloud platform for observation. It also offers prompt notifications to assist in mitigating flood-related dangers and enhance early warning measures.

   In system [3], Water pressure sensors are used by the affordable pressure sensor-based flood monitoring system with IoT to precisely measure rising water levels. For tracking and analysis in real time, the data is sent to an IoT platform. This method provides an affordable and dependable way to detect floods early and send out timely alerts.

   This system [4] In this study, Flood forecasting employs machine learning methods that utilize past rainfall, water level, and climate information to anticipate upcoming flood occurrences. Techniques like ANN, SVM, and Random Forest examine patterns and enhance prediction precision. These models assist officials in making prompt choices and minimizing flood-associated hazards

   The research on GIS difficulties in handling flash floods in Shah Alam emphasizes problems like scarce real-time data, obsolete spatial maps, and irregular data integration. Technical limitations and poor coordination among agencies diminish GIS efficiency. These obstacles impede precise flood forecasting, strategic planning, and swift reactions. [5].

   This research [6] A real-time flash flood monitoring and forecasting system driven by IoT utilizes sensors to constantly monitor water levels, rainfall, and flow conditions. Information is transmitted immediately to cloud services for examination and timely forecasting. This system enhances quick alerts, boosts safety, and facilitates prompt disaster response.

3. OBJECTIVE

   The purpose of this work is to design and build a highly dependable data transmission system capable of preserving data integrity in fault-prone and safety-critical situations. The

   work intends to do this by combining Triple Modular Redundancy (TMR) for disguising hardware defects with CRC-based error detection, notably CRC-16, to effectively detect transmission mistakes. The system is written in Verilog HDL to enable real-time hardware implementation, and its performance is assessed using simulation and fault injection tests. Overall, the goal is to show that combining TMR and CRC yields a reliable, scalable, and practical solution for fault-tolerant communication in mission-critical applications.

4. PROPOSED SYSTEM

   The suggested system combines Triple Modular Redundancy (TMR) and CRC-16 error detection to create a dependable and fault-tolerant data transmission method for safety-critical applications. In this architecture, input data is initially encoded with CRC-16 to produce a checksum that allows for

   accurate detection of single-bit and burst mistakes. The CRC- encoded data is subsequently processed by three identical modules that run in parallel under the TMR framework. Each module generates an independent output, and any mismatch is handled by a majority voter, who chooses the correct result based on majority agreement, successfully hiding single- module defects. At the receiver end, CRC-16 verification verifies that the transmitted data was not corrupted during communication.

   1. METHODOLOGY

      The approach for developing and implementing the fault- tolerant data transmission system consists of multiple structured steps, beginning with requirement analysis and progressing to hardware description, simulation, and performance evaluation. The system uses Triple Modular Redundancy (TMR) and Cyclic Redundancy Check (CRC) to ensure error masking and detection during data transfer.

      System Requirements and Architecture Design: The process begins with determining the dependability requirements for mission-critical applications like aircraft and industrial automation. According to these requirements, the system is divided into functional blocks: the CRC generator, CRC checker, TMR encoder, TMR majority voter, and data transmission channel. A high-level architecture is developed to demonstrate how data is routed through the CRC module for error detection and the TMR logic for redundancy and correction.

      CRC-16 Error Detection Module Design: The CRC module is based on the standard CRC-16 polynomial (0x1021).The CRC encoder uses input data to build a 16-bit CRC sequence. Prior to transmission, the CRC bits are inserted to the encoded data. On the receiving end, the CRC decoder recalculates the CRC value and compares it to the received CRC to detect any transmission mistakes. To ensure efficiency, the CRC logic is written in Verilog utilizing linear feedback shift register (LFSR) techniques. This system's primary objective is to combine Triple Modular Redundancy (TMR) with high data transmission reliability.

      with error detection based on CRC. TMR is a fault-tolerant method that replicates the essential parts of the system in three parallel routes, enabling majority voting to fix any mistakes. Conversely, CRC is a proven error-detection technique that makes it possible to identify unintentional modifications in raw data as it is being transmitted.

      1. The following goals were considered when designing the system architecture:

         Tolerance for Faults: By choosing the majority vote from the three channels, TMR guarantees that the system can continue to function properly even if one of the modules fails because of noise, interference, or hardware issues.

         Data Integrity: Bit flips and data corruption are examples of faults that can be identified at the receiving end thanks to the CRC algorithm.

         Scalability: Because the architecture is modular, it is simple to adapt to different systems by changing the CRC parameters or the number of redundant modules.

      2. Cyclic Redundancy Check (CRC) Encoder Design: An essential part of the system that computes and adds a CRC checksum to the original data is the CRC Encoder. The generator polynomial determines the type of CRC that is used (e.g., CRC-16-ANSI). CRC is based on polynomial division, where the transmitted message is viewed as a polynomial.

         CRC encoding involves the following steps: fts and XOR operations, iterating over every data bit. The CRC is first set to a predetermined value (for example, 0xFFFF for CRC-16) and is updated using the selected polynomial for each bit of data.

         CRC Appending: After the CRC has been computed, it is added to the original data to create the encoded data, which is subsequently sent over the communication channel. The CRC encoder continuously processes data in the Verilog implementation of the CRC16 Sender module. In order to provide the right encoded output, the module makes sure that the CRC is updated anytime the input data changes.

      3. Triple Modular Redundancy (TMR) and Data Transmission: Three identical copies of the data transmission system are made in the TMR-based system. The same input data is processed by each duplicate, producing an encoded output that includes the data and the CRC. Modules 1, 2, and 3 are the names given to the three identical systems.

         The fundamental principle of TMR is that the receiver can use the majority voting logic to reconstruct the correct data even if one of the modules introduces an error (caused by defects like bit-flips or noise).

         For instance: In the event that module 1 sends accurate data but module 2 or module 3 encounter faults, the recipient will select the TMR is an efficient option for fault-tolerant systems since it offers resilience to single sources of failure, guaranteeing that the right data is chosen.

         Because each data transmission channel (module) is independent, errors in one module won't impact the others.

         Through the transmission channel, the three modules simultaneously transfer their encoded data.

      4. Majority and Receiver Design Voting Logic: Three identical encoded data streams can be handled by the system at the receiver end. Every stream of encoded data is made

         from of the information and the CRC that goes with it. The receiver's main job is to perform CRC validation, which involves extracting the data and CRC from each of the three encoded data streams that were received. After that, it recalculates the received data's CRC and compares it to the received CRC. An error in the received stream is indicated if there is a mismatch.

         Majority Voting: The majority voting mechanism is used if a single fault is found in one of the streams. The receiver determines which of the three received data values is correct by comparing them. By selecting the majority value from the other two channels, this guarantees that the system can still recover the correct data even in the event of a fault in one channel.

         Error Detection: The system flags an error if all three streams are faulty or if most of the received data values are different. In this instance, the recipient provides a predetermined error value to indicate a critical failure, such as 0xDEAD.

         This method ensures that the system can continue to transmit data reliably and that any single-point failure will not result in data corruption.

      5. Fault Injection and Simulation: Extensive fault injection simulations were conducted to examine how the system reacts to different failure scenarios in order to verify the efficacy of the fault tolerance mechanism. At several stages of the data transmission process, faults were introduced, including: Single-bit mistakes: During transmission, faults were created by flipping individual data bits. The CRC identified these

      problems and used majority vote to fix them.

      Burst errors: To simulate situations where noise or interference could influence the transmission, a sequence of successive bit mistakes was created.

      Block Diagram

      Figure 4.1.2

      Single-bit mistakes: During transmission, faults were introduced by flipping individual bits of data. The CRC identified these problems and used majority vote to fix them.

      Burst errors: To simulate situations where noise or interference could influence the transmission, a sequence of successive bit mistakes was created.

      Comparison of Other Fault-Tolerant Designs:

      TMR CRC is comparable to other fault-tolerant systems like Quorum and N-version programming.

      Quorum-based: Scaling systems that require a majority decision from replicas can be computationally intensive and complex to manage.

      N-version programming uses numerous copies of the same program to handle software flaws, but it adds significant overhead and complexity.

      TMR-CRC is a simple, hardware-agnostic solution to fault tolerance that balances reliability and system economy. The system functioned well under all failure scenarios, with robust fault tolerance and excellent error detection accuracy, as verified by functional verification and performance analysis using Vivado.

      The final phase in the design technique is to evaluate the system's performance. Key performance indicators include: Accurate error detection and output:

      Throughput: The rate at which data may be sent and decoded while retaining reliability.

      Latency is the delay caused by the fault detection and recovery method. The TMR system's processing of three data streams may increase latency relative to non-redundant systems. However, the benefits of fault tolerance outweigh this modest increase.

5. RESULTS AND DISCUSSION

   We designed and implemented a fault-tolerant data transmission system with triple modular redundancy (TMR) and CRC-based error detection.

   The system uses CRC-16 error checking and TMR to assure data integrity and reduce single points of failure during transmission. Verilog HDL was used for implementation, and validation was done through simulation using a test bench that simulates real-world data transmission scenarios with potentialerrors.

   Fig 4.1.3 Simulation Results

   Fig 4.1.4 Implementation Results

   The simulation results demonstrated the system's reliability in fault-tolerant data transmission.

   Reliable data transmission is critical in today's communication systems, as seen in Figure 4. Implementation Results for scenarios that require high fault tolerance. This paper provides a fault-tolerant data transmission scheme that employs Triple Modular Redundancy (TMR) to ensure error resilience. The architecture uses Cyclic Redundancy Check (CRC) for error detection, combining the benefits of both approaches to improve dependability.

6. OUTPUT

   The "Design and Implementation of Reliable Fault-Tolerant Data Transmission Using Triple Modular Redundancy and CRC-Based Error Detection" project displays satisfactory results.A fault-tolerant communication system employs TMR and CRC-based error detection. Using TMR improves data

   transmission reliability by ensuring that even with defects, the majority decision mechanism selects the correct data. The CRC-based error detection method effectively detects transmission faults, improving the system's ability to detect differences in sent data. Combining TMR and CRC offers reliable protection against both transient and persistent defects, essential for mission-

7. CONCLUSION

The "Design and Implementation of Reliable Fault-Tolerant Data Transmission Using Triple Modular Redundancy and CRC-Based Error Detection" project successfully demonstrates a fault-tolerant communication system utilizing TMR and CRC-based error detection. Using TMR improves data transmission reliability by ensuring that even with defects, the majority decision mechanism selects the correct data.

By effectively detecting transmission defects, the CRC-based error detection method improves the system's capacity to discover any disparities in the sent data. For mission-critical applications including aircraft, automotive, and industrial systems, the combination of TMR and CRC offers strong protection against both transient and persistent failures.

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