Designing a XOR Gate Circuit based on Floating Gate and Quasi-Floating Gate

DOI : 10.17577/IJERTV5IS050717

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  • Total Downloads : 232
  • Authors : Chetna Verma, Preeti Singh, Ms. Shobha Sharma
  • Paper ID : IJERTV5IS050717
  • Volume & Issue : Volume 05, Issue 05 (May 2016)
  • DOI :
  • Published (First Online): 21-05-2016
  • ISSN (Online) : 2278-0181
  • Publisher Name : IJERT
  • License: Creative Commons License This work is licensed under a Creative Commons Attribution 4.0 International License

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Designing a XOR Gate Circuit based on Floating Gate and Quasi-Floating Gate

1Chetna Verma, 2Preeti Singh, 3Ms Shobha Sharma Department of Electronics & Communication Engineering Indira Gandhi Delhi Technical University for Women New Delhi India

Abstract- Nowadays important parameter in designing analog and digital circuits is reducing power consumption of the circuit. In analog and digital circuit power dissipation is given by P=CfV2 which shows power is directly proportional to square of voltage. So power consumption can be decreased by reducing the voltage supply. Another importance of low voltage is that circuits are easy to transport because the small battery is used as the voltage supply on them.

Keywords: CMOS, low voltage, floating gate, quasi floating gate, power consumption, PSPICE.


    The CMOS digital circuits with very low power consumption and high operating speed have always been the focus of the design criteria. Since there is always a trade-off between power dissipation and time delay in digital circuits, so reducing the power dissipation and still maintaining the high performance of circuits in terms of speed is important in digital designs. There is a need for new design techniques for optimum performance of devices to be operated at sub-volt supplies and consuming very low power with the continuous reduction of their dimensions. The power supply reduction is must with scaling down of devices but it happens at the expense of speed. Since the performance of circuits can be altered with tuning of threshold voltage of transistors, therefore FGMOS has been abundantly employed to enhance the performance of mixed mode low voltage circuits despite their inherent limitations like reduced gain-bandwidth product and large chip area due to the need of large biasing capacitance. The use of Quasi-floating gate MOSFET (QFGMOS) can further enhance the performance of circuits in terms of high speed and low power dissipation as compared to FGMOS. It is because of the fact that QFGMOS doesnt need a large biasing capacitance as its gate is feebly connected to supply voltage through a large value resistor.


    The first appearance of floatinggate technique was in 1967. In the late 1980s, the Intel ETANN chip employed it as an analog nonvolatile memory element. From that date, floatinggate devices are finding wider applications by analog researchers. A number of papers have been reported in the literature for applications of floatinggate technique in analog circuits, such as floating gate CMOS analog trimming circuits , neural network components, multipliers

    , D/A converters , amplifiers, operational transconductance amplifiers , and differential voltage current conveyors .

    These devices can be fabricated in all CMOS technologies, but a double poly CMOS technology is preferred. In FGMOS, the gate is fabricated using the gate electrode (poly1) layer and is surrounded by two SiO2 insulator layers thus electrically isolated from the rest of the device.

    The device inputs are placed on top of the upper SiO2 insulating layer and are fabricated using another conducting layer, preferably a second layer of polysilicon (poly2). Thus, from the dc operating point of view, the gate is floating node, and that is why the MOS is called floatinggate MOS. Inputs are capacitively coupled to the FG, and the sizes of the input electrodes determine the values of the capacitors, which can be varied according to the designers needs. The circuit symbol, equivalent circuit, layout, and crosssection of a two input floating gate NMOS are shown in Fig.1.

    Fig 1: Two-input floating-gate NMOS: (a) symbol, (b) equivalent circuit, (c)layout and (d) cross section

    Cfgd, Cfgs, and Cfgb denote the parasitic capacitances from gate to drain, source, and bulk,

    respectively, CGi is the coupling capacitance of the ith input branch, the term CTOTAL refers to the total capacitance seen by the FG and is given by:

    Assuming zero initial charge and neglecting parasitic capacitances as compared to Cbias and Cin, the gate voltage of MOS

    The equivalent threshold voltage for the MOS adjusts itself to a new value VT,eq

    The transition frequency equation of FG MOS

    It is clear that the transition frequency of FG MOS is smaller than the transition frequency of GD MOS; hence FG MOS has smaller bandwidth than conventional MOSFET.

    Fig 2: XOR gate using FGMOS technique


    To overcome the main problems of the floatinggate MOS, namely the initial charge trapped in the floating gate problem and the large silicon area problem, a quasi floatinggate MOS (or pseudofloatinggate MOS) is an appropriate solution. Applications based on QFGMOS

    include: differential operational amplifiers, transconductors, current mirrors, filters, current conveyors, and linear MOS resistors.

    Floatinggate MOSs use voltage dividers with relatively large attenuation factors at the transistor gates to reduce supply requirements. The dividers use large capacitance to set the floating gate DC voltage close to one of the supply rails. Unfortunately, this large capacitance leads to an increase in silicon area and a reduction of the effective transconductance and gainbandwidth product (GBW). Besides, as mentioned before, some technique is required to avoid the initial charge trapped in the floating gate.

    All these issues are solved by weakly connecting the floating gate to a proper DC voltage using a largevalued resistor which can be implemented by the leakage resistance of a reversebiased junction of a diode connected MOS transistor operating in cutoff region. Therefore, this pullup or pulldown resistor Rleak sets the DC gate voltage to a power rail, thus preventing initial charge issues and simultaneously minimizing the supply voltage requirements.

    The large resistance value employed makes the gate effectively floating from signal frequencies of above 0.05 Hz so that AC operation is unaffected even for very low frequencies. At the same time, GBW degradation effects are avoided since a large biasing capacitor is no longer required.

    The symbol of single input terminal QFG MOS (a), its equivalent circuit (b) and layout (c) are shown in Fig. 3. The input terminals are capacitively coupled to the quasi floating gate, but the DC gate voltage is set to Vbias without requiring a large capacitor.

    The pullup or pulldown resistor can be implemented in practice by the large (and nonlinear) leakage resistance of reversebiased pn junction of MOS transistor operating in cutoff region, as shown in Fig. 3. This fact leads to significant savings in terms of area compared to the MIFG device.

    Fig 3: One-input-floating gate NMOS: (a) symbol, (b) its equivalent circuit and(c) layout

    Cfgd, Cfgs and Cfgb denote the parasitic capacitances from gate to drain, source, and bulk respectively, Ck is the coupling capacitance of the kth input branch, and CTOTAL is the total capacitance and is given by:

    Due to a large value of Rleak, even at low frequencies. A simple analysis reveals that the AC voltage at the floating gate is given by

    The transition frequency can be expressed by

    The input referred noise of QFG MOST is smaller than it of FG MOST, since CTOTAL, QFG <CTOTAL, FG.

    Fig 4: XOR Gate Using Quasi Floating Gate Technique


    The performance of the FGMOSFET and QGMOSFET was verified by PSpice simulations with supply voltage 0.8V using 0.35um CMOS technology parameters.

    Fig 5: Transient analysis of GMOS XOR gate

    Fig 6: Output current Vs applied voltage

    Fig 7: Power Dissipation FGMOS XOR gate

    Fig 8: Transient analysis of QGMOS XOR gate

    Fig 9: Output current Vs applied voltage in QGMOS

    Fig 10: Power Dissipation in QGMOS XOR gate

    floating gate circuits by which we could take advantages of floating gate technology while the disadvantages would be decreased.

    Table1. Comparison of XOR gate with FGMOS and QGMOS technique

    Propagation Delay (n sec)

    Power Dissipation( mWatt)

    PDP (p-


    Req(K ohm)




    gate using FGMOS







    gate using QGMOS







In this paper, we have briefly described FGMOS and QGMOS and used it to implement a XOR gate. The characteristics of QGMOS-based XOR gate is compared with those of FGMOS counterpart. It was found that QGMOS simulates a higher value of resistance, offers lager bandwidth as compared to FMOS version due to its inherent advantage and consumption of less power. The Pspice simulation results were found to be in conformity with the theory.

Fig 11: Comparative resistance simulation characteristics

Fig 12: Comparative frequency response of QGMOS and FGMOS

The simulation has been implemented using two different techniques i.e. Floating gate and Quasi Floating gate. It can be seen from figure[6] and [9] that QGMOS and FGMOS technique require less voltage for operation .The comparative resistance simulation characteristics of VCR based on FGMOS and QGMOS shown in Figure [11] Req for FGMOS IS 1.30Kohm whereas it is 1.48Kohm for QGMOS-based XOR gate. The comparative frequency response of QGMOS and FGMOS based XOR gate is shown in Figure [14].The bandwidth of QGMOS-based XOR gate is found to be 3.62GHz, which is greater than that of FGMOS based XOR gate due to absence of large capacitance. From table [1] it can be seen that power dissipation for QGMOS technique is less as compared to FGMOS and power delay product of QGMOS based XOR gate is less as compared to FGMOS based XOR gate. As a consequence, QGMOS circuits are a better choice for being used in supply voltages in which the circuit involves threshold voltage, also these circuits on the basis of power dissipation are recommended to be used in this situation. Modern methods are recommenced to design Quasi


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