 Open Access
 Total Downloads : 650
 Authors : Yellaboina Venkateswarlu
 Paper ID : IJERTV2IS90136
 Volume & Issue : Volume 02, Issue 09 (September 2013)
 Published (First Online): 10092013
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Design of the 40MHz Double DifferentialPair Cmos OTA with 60db IM3
Design of the 40MHz Double DifferentialPair Cmos OTA with 60db IM3
Yellaboina Venkateswarlu PG Student
Department of Electronics and Communication Engineering, Sree Nidhi Institute of Science and Technology, Hyderabad.
AbstractA configuration of a linearized operational transcon ductance amplifier (OTA) for lowvoltage and highfrequency applications is proposed. By using double pseudo differential pairs and the sourcedegeneration structure under nanoscale CMOS technology, the nonlinearity caused by short channel effect from a small feature size can be minimized. A robust commonmode control system is designed for input and output commonmode stability and thus reduces distortion caused b y commonmode voltage variation. Tuning ability can be achieved by using MOS transistors in the linear region. The linearity of the OTA is about
60dB thirdorder intermodulation (IM3) distortion for up to 0.9 pp at 40 MHz. This OTA was fabricated by the TSMC 180nm deep nwell CMOS process. It occupies a small area of

10 3 mm2 and the power consumption is 9.5 mW under a 1.5V supply voltage.
Index TermsOperational transconductance amplifier (OTA), pseudodifferential structure, short channel effect, source degeneration.

INTRODUCTION
HE operational transconductance amplifier (OTA) is one of the most important building blocks in analog and mixed
mode circuits, including multipliers [1], [2], continuoustime
– filters [3], [4], voltagecontrolled oscillators (VCOs) [5], and continuoustime sigmadelta modulators [6]. Its main idea is to convert the input voltage into the output current with a linear transformation factor. The active device is used for re placing passive devices owing to power and area consideration with the tradeoff of linearity. However, as the feature size of CMOS technology scales down with power supply voltage, the dynamic range, bandwidth, and power consumption will be limited by the linearity performance. A variety of lin earization techniques have been reported in recent years [7]. Most of them exploit the ideal squarelaw behavior of the MOS transistor in the saturation region to obtain highlinearity conversion. Unfortunately, this concept is not quite suitable for small feature sizes of MOS transistors due to the in fluence of secondorder effects like velocity saturation and mobility reduction
The use of multipleinput floatinggate (MIFG) MOS tran sistors was also presented recently [8], [9]. The natural attenu
ation could be obtained from the designed capacitor ratio. The MIFG circuit would act as a voltage divider and thus result in a large linear input swing range.
In this paper, we present a highlinearity and highspeed
OTA. It makes use of two input transistor pairs with their source terminals connecting to resistor loads and the drain terminals crosscoupled to each other. In the approach, high linearity can be achieved by choosing different values of loading resistors. The model of the short channel effect and the nonlinearity analysis of CMOS transistors are described in Section II, and the proposed OTA implementation is pre sented in Section III. The analysis of nonideal effects such as mismatch and noise performance of the proposed circuit are discussed in Section IV. Section V shows the measured perfor mance of fabricated implementation. Finally, conclusions are drawn in Section VI.

NON LINEARITY ANALYSIS OF SATURATED MOS TRANSISTORS

Linearized Characteristic
The relationship of the voltagetocurrent conversion could be described as , where and are the input voltage and the output current, respectively. The ideal assump tion of the linearized transformation is , where is a constant within the applied input voltage range. Unfortunately, the conversion is not possible to be perfectly linear in real circuit implementation, and the conversion can be inves tigated by a Taylor series expansion. If the differential structure is applied with wellmatched implementations, which means the evenorder terms can be cancelled out, the current conversion can be expressed by
(1)
where the coefficients are determined from the circuit im plementation. If the nonlinear factor is suppressed, that is, the parameters are minimized, the conversion would be close to a linear function, as demanded.
Fig. 2. Nonlinearity cancellation using double pseudodifferential pairs with de generation resistors.
Fig. 1. Pseudodifferential circuit by taking shortchannel effects into consider ation.

Saturated MOS Transistor Under NanoScale CMOS Technology
Linear conversion is usually developed based on the basic squarelaw behavior of the MOS transistor in the satura tion region [1] as
sourcedegenerated resistors are added up to simplify the ex pression. Assume that transistors M1M4 are operated in the saturation region and that and are the input differential signals, which would be composed of commonmode and dif ferentialmode voltages
(2)
where , and are the width and length of the device, respectively, is the oxide capacitance per unit channel area, is the lowfield mobility, and is the nMOS threshold voltage. However, this condition only holds for the large length of MOS transistors. As the device size is scaled
(4)
where is the input commonmode voltage and is the input differentialmode voltage. Then, the output current of each transistor could be given by
down towards nanoscale CMOS technology, the shortchannel effect occurs due to the transversal and longitudinal electric
fields. Thus, with the enhancement of speed and area for small device length, the linearity of conversion based on the ideal squarelaw equation becomes deteriorated. Fig. 1(a) shows the circuit of the pseudodifferential input pair [12]. If the length of the MOS transistors is chosen to be the minimum feature size
under nanoscale CMOS technology, the output drain current can be modeled by
(5)
(3)
where is the mobility reduction coefficient. From the equation shown above, the mobility reduction coefficient can be mod eled by a resistor connected to the source terminal of an ideal MOS transistor, as shown in Fig. 1(b). The value of the equivalent resistor is equal to . Moreover, the linearity per formance degrades for larger . This is confirmed by the results presented in [13], where tunable resistors are introduced in the source terminals of the pseudodifferential pair for the use of transconductance tuning ability with the expense of additional distortion. In this paper, in order to resist the nonlinearity which occurs by the shortchannel effect, the double differential pairs with a sourcedegeneration structure are adopted, as shown in Fig. 2. In the proposed structure, two different values of re sistors and are used for each differential pair, and the
where , , , and . Thus, under ideal matching, the differential output current would be the function of the input signals
(6)
where is the thorder harmonic component provided by the th transistor of the proposed structure, , and . Although the resistors connected to the source of a single pseudodifferential pair degrade the lin earity performance, the thirdorder harmonic component could be cancelled out by proper sizing of the double pseudodifferen tial pairs through a Taylor series expansion of (6) to yield
This expression can be obtained by giving
(8)
were , , and is the width, length, and transconduc tance of the th transistor, respectively, and is the th short channel equivalent resistance. Under the minimization of the thirdorder harmonic component, the transconductance of the proposed structure is given by
(9)
The transconductance decreases because of introducing the double differential pairs and the sourcedegeneration resistors. This implies higher linearity with the tradeoff of higher power consumption.

Design Methodology
In order to obtain highlinearity performance for the double differential pair structure under optimal transconductance effi ciency, a simple approach is used by giving the ratio of param eters to represent the circuit operation. Thus, by giving
(10)
we can find that the ratios of (10) would be used to define the transconductance efficiency compared with the single differen tialpair circuit and the thirdorder harmonic component of the proposed circuit. In addition, the ratio values should be designed within practical implementation boundary. Bandwidth, noise performance, and matching are also taken into consideration.
The optimization procedure starts from the reduced transcon ductance value. We define that less then 30% of the transconduc tance should be reduced with respect to that of a single differen tialpair circuit with the same size and current consumption. From Fig. 3, we can find that, if the value of is set to 3 under large , we can obtain less than 30% reduction of the transconductance. Moreover, if the value of 4 for is used, less than 25% reduc tion of the transconductance would be obtained. Fig. 4 shows the thirdorder distortion component of the proposed design. In order to obtain minimized distortion components, the ratio is chosen as 9 while is set to 3. If is set to 4 for less transconductance reduction, should be set to 16, but such a large ratio would de grade the bandwidth performance owing to the large parasitic ca pacitance of input transistors. After the optimization procedure, the optimal ratios of the proposed circuit would be given by
(11)
The optimization procedure concludes that the thirdorder dis tortion component is ideally cancelled out with the expected
Fig. 3. Optimal parameter evaluation for the reduced transconductance.
Fig. 4. Optimal parameter evaluation for the thirdorder harmonic component.
transconductance value, as shown in Fig. 5. The linearity per formance is actually robust to process variation owing to the flat distribution in Fig. 4. Thus, the small reduction of the transcon ductance value makes high linearity and high speed possible under about 30% of extra power consumption.
Transconductance tuning would be another important issue in the OTA design. The main idea of the transconductance tuning is to compensate for the variation caused from fabricated process and temperature. Fig. 5 shows the contour plot of the thirdorder harmonic component under transconductance tuning, resulted from Fig. 4. We can find that, if is changed from 1 to 4 when is set to 9, it implies more than 300% of the transconductance tuning range, as shown in Fig. 3, and the thirdorder harmonic component value of less than 0.001 can be guaranteed, as illus
trated in Fig. 5.


PROPOSED OTA CIRCUIT

Implementation of the Linearization Technique
Fig. 6 shows the proposed OTA design. Two differential pairs M1M2 and M3M4 are used in order to cancel the nonlinearity component, as described in the previous section. For continuous
Fig. 5. Contour plot for the thirdorder harmonic component under transcon ductance tuning.
Fig. 6. Proposed OTA circuit.
transconductance tuning strategy, transistors M5M8 operating in the linear region are used to replace the resistors. The equiv alent resistance is given by
(12)
where is the gate voltage of the transistor. Therefore, we can obtain the required equivalent resistance by applying the voltage and to yield
(13)
(14)
The linearity can be maintained by proper sizing of the de generated transistors and the control voltage. In addition, the tuning ability of the proposed circuit can be achieved by ad justing the control voltages and . Fig. 7 shows the simu lated largesignal transconductance of the differential OTA op erating in a 1.5V supply voltage. The proposed circuit can be tuned from 360 to 470 S. It can be noticed that the transcon ductance tuning range is limited by the linearregion operation of transistors M5M8. Besides, the speed of the proposed OTA is mainly limited by the parasitic capacitors caused by the cur rent mirror circuits.
Fig. 7. Simulated transconductance tuning range.

CommonMode Stability
The OTA shown in Fig. 6 requires a proper commonmode control system due to the pseudodifferential structure [14], [15]. The commonmode control system includes the commonmode feedforward (CMFF) circuit and the commonmode feedback (CMFB) circuit. The CMFF circuit should be used with the CMFB circuit for output commonmode voltage stabiliza tion. Fig. 8 shows the circuit of the commonmode control system. For the CMFB circuit, the input transistors MF1MF4 perform the tasks of the commonmode detection and refer ence comparison. If the commonmode voltage of the OTA output signal equals the desired commonmode voltage , then the total current through MF7 will be constant and the commonmode bias voltage VCM is fixed. On the other hand, if the commonmode voltage of the OTA output signal is not the same as , a current will be mirrored by MF9 to change VCM adaptively. Thus, the feedback mechanism adjusts the output commonmode voltage to the desired value.
Furthermore, the input commonmode control circuitry is formed by transistors MF14MF18 that constitute the CMFF circuit. The combination of transistors MF14 and MF15 gen erates a scaled copy of input commonmode currents, which is subtracted at the OTA output stage through the use of current mirror MF17MF18. Thus, the input commonmode signal could be suppressed out and only the differentialmode signal appears at the output stage. As the mechanism shown above, it is demonstrated the commonmode control circuit can be implemented to achieve excellent stability over the tuning range. Moreover, linearity could be maintained by the robust and stable commonmode control system.
The commonmode rejection (CMR) depends on matching. We can define a matching factor of ( ) between the
CMFF path and the signal path, where is the mismatch
ratio. We can emulate the CMFB circuit as a small resistor of value , and then the commonmode gain
of at low frequency can be obtained, where is obtained from (9), is the transconductance of transistors M17 and M18, and is the output conductance of the OTA. This is the result of the combined CMFB and CMFF systems. Because is large and is much less than unity,
even mis match problems occur so that high CMR can be obtained.
Fig. 8. Commonmode control system.


NONIDEALITY ANALYSIS OF THE IMPLEMENTATION

Mismatch
Owing to the nonideal matching phenomena of MOS tran sistors, the nonlinearity cancellation is not perfect and second order harmonic distortion components would still appear at the differential output nodes. For the double differentialpair struc ture, it is assumed that there are mismatches of
for transistors M1 and M2 and for transistors M3 and M4. Repeating the analysis of (6), we can find that the secondorder distortion component resulted from mismatch is given by

Thermal Noise
For the highspeed circuit, the most significant noise source of a single transistor is the thermal noise rather than the flicker noise. The channel noise can be modeled by a current source connected between the drain and source with a spectral density
(16)
where is the Boltzmann consant, is the absolute temper ature, is the source conductance, and the device noise pa rameter depends on the bias condition [16]. Using the thermal noise model, the total outputreferred noise spectral density of the double differential pairs with degeneration structure is de rived as
(15)
Therefore, the distortion components caused by transistor mis match could be minimized by applying large degenerated re sistors and gate overdrive voltage. Besides, the current mirrors M9M12 would also contribute secondorder distortion compo nents under the proposed degenerated structure, and thus large device sizes and small aspect ratios would be designed. From the simulation with 2% transistor mismatch, the highest even order components remain lower than oddorder components by at least 5 dB. In addition, careful layout was taken while the de vice match is required. The error output current contributed by transistor mismatch can be divided by the overall transconduc tance to model an equivalent offset voltage, and it could be re moved by applying an offset voltage of input differential signals.
(17)
where and would be the noise parameter at saturation and linear regions, respectively. The inputreferred noise spectral density could be calculated by dividing the output referred noise
Fig. 9. Die microphotograph.
spectral density by the overall OTA transconductance. From the noise analysis, large aspect ratios of input transistors and small aspect ratios of load transistors should be designed. The inputreferred noise of the proposed circuit is higher than the single differentialpair circuit owing to the fact that the noise contribution is the combination of two input differential pairs. Moreover, the degenerated MOS resistors contribute additional noise sources to the proposed circuit.


EXPERIMENTAL RESULTS
The proposed OTA has been fabricated with TSMC 180nm deep nwell CMOS process. It has been measured to verify its operation and to evaluate the linear characteristics. A mi crophotograph of the linear OTA is depicted in Fig. 9, and the oc cupied area is 15.1 mm . A supply voltage of 1.5 V was employed in the measurements, and the nominal static power consumption of the OTA is 9.5 mW. The required supply voltage for the circuit is (saturation region), and 1.5 V is suf ficient for this circuit to operate under 180nm CMOS process. For the measurement setup, the output signal of the signal generator was past through a low pass filter for the spectral purity of the input signal. The transformers were used before and after the input and output terminals for singletodiffer ential and differentialtosingle conversion for the differential circuit. The output signal was measured with a spectrum ana lyzer. The thirdorder intermodulation (IM3) distortion mea sured with two sinusoidal tones of 0.9 amplitude is shown in Fig. 10. The IM3 is shown to be about 60 dB at a speed of 40 MHz. Fig. 11 shows the nonlinearity behavior with re spect to the frequency under the same input swing range. At low frequencies, the IM3 of dB could be obtained. More over IM3 less than ould be achieved for a frequency up to 60 MHz. The increment of the IM3 is due to the different high frequency behaviors of the two input differential pairs. The measured input referred noise spectral density at 40 MHz is
Fig. 10. Measured twotone intermodulation distortion.
Fig. 11. Measured twotone intermodulation distortion with respect to input signal frequency.
nV Hz. Table I summarizes this work with recently re ported works. In order to compare with different implementations of OTAs, the defined figure of merit (FOM), which takes the transconductance value, linearity performance, speed of the implemented circuit, input swing range, and power consump tion into account, is expressed as follows:
(18)
Therefore, our highspeed linear OTA compares favorably with the literature.

CONCLUSION
An approach to enhance the OTA linearity under nanoscale technology has been proposed, and the experimental result proves the same linear characteristic by the fabricated
chip. By taking the shortchannel effect into consideration under small feature sizes, this approach is based on the nonlinearity cancellation scheme with two pseudodifferential pairs of the sourcedegeneration structure, and the circuit performs well at high frequencies. The MOS transistors working in the linear region were used to replace the poly resistors. It not only saves the chip area but also adds the tuning ability. A commonmode control circuitry, including the CMFF and CMFB circuits, is used for the input and output common mode stability. The measurement results show about 60dB IM3 with 40MHz
0.9 input signals under a 1.5V supply voltage.
ACKNOWLEDGMENT
The authors would like to thank the National Chip Implemen tation Center of Taiwan for supporting the chip fabrication.
REFERENCES

M. Ismail and T. Fiez, Analog VLSI Signal and Information Pro cessing. New York: McGrawHill, 1994.

S. R. Zarabadi, M. Ismail, and C. C. Hung, High performance analog VLSI computational circuits, IEEE J. SolidState Circuits, vol. 33, no. 4, pp. 644649, Apr. 1998.

C. C. Hung, K. A. Halonen, M. Ismail, V. Porra, and A. Hyogo, A lowvoltage, lowpower CMOS fifthorder elliptic GM C filter for baseband mobile, wireless communication, IEEE Trans. Circuits Syst. Video Technol., vol. 7, no. 4, pp. 584593, Aug. 1997.

T. Y. Lo and C. C. Hung, A wide tuning range G C continuous time analog filter, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 4, pp. 713722, Apr. 2007.

J. Galan, R. G. Carvajal, A. Torralba, F. Munoz, and J. RamirezAn gulo, A lowpower lowvoltage OTAC sinusoidal oscillator with a large tuning range, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 2, pp. 283291, Feb. 2005.

J. van Engelen, R. van de Plassche, E. Stikvoort, and A. Venes, A sixthorder continuoustime bandpass sigmadelta modulator for digital radio IF, IEEE J. SolidState Circuits, vol. 34, no. 12, pp. 17531764, Dec. 1999.

D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997.
Vol. 2 Issue 9, September – 2013

E. RodriguezVillegas, A. Yufera, and A. Rueda, A 1.25V microp ower G C filter based on FGMOS transistoes operating in weak in version, IEEE J. SolidState Circuits, vol. 39, no. 1, pp. 100111, Jan. 2004.

A. E. Mourabit, G.N. Lu, and P. Pittet, Widelinearrange sub threshold OTA for lowpower, lowvoltage, and lowfrequency applications, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 8, pp. 14811488, Aug. 2005.

A. J. LopezMartin, S. Baswa, J. RamirezAngulo, and R. G. Carvajal, Lowvoltage super class AB CMOS OTA cells with very high slew rate and power efficiency, IEEE J. SolidState Circuits, vol. 40, no. 3, pp. 10681077, Mar. 2005.

A. Demosthenous and M. Panovic, Lowvoltage MOS linear transcon ductor/squarer and fourquadrant multiplier for analog VLSI, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 9, pp. 17211731, Sep. 2005.

A. N. Mohieldin, E. SÃ¡nchezSinencio, and J. SilvaMartÃnez, A fully balanced pseudodifferential OTA with commonmode feedforward and inherent commonmode feedback detector, IEEE J. SolidState Circuits, vol. 38, no. 4, pp. 663668, Apr. 2003.

X. Fan and P. K. Chan, An enhanced adaptice Qtuning scheme for a 100 MHz fully symmertic OTAbased bandpass filter, IEEE J. Solid State Circuits, vol. 38, no. 4, pp. 585593, Apr. 2003.

M. Chen, J. SilvaMartÃnez, S. Rokhsaz, and M. Robinson, A 2V
80200MHz fourthorder continuoustime linear phase filter with au tomatic frequency tuning, IEEE J. SolidState Circuits, vol. 38, no. 10, pp. 17451749, Oct. 2003.

T. Y. Lo and C. C. Hung, A high sped and high linearity OTA in 1V power supply voltage, in Proc. ISCAS, 2006, pp. 18641867.

U. Yodprasit and C. C. Enz, A 1.5V 75dB dyamic range third order G C filter integrated in a 0.18 m standard digital CMOS process, IEEE J. SolidState Circuits, vol. 38, no. 7, pp. 11891197, Jul. 2003.

I. S. Han, A novel tunable transconductance amplifier based on voltagecontrolled resistance by MOS transistors, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 8, pp. 662666, Aug. 2006.

A. Lewinski and J. SilvaMartÃnez, OTA linearity enhancement tech nique for high frequency applications with IM3 below 65 dB, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 51, no. 10, pp. 542548, Oct. 2004.

A. J. LopezMartin, J. RamirezAngulo, C. Durbha, and R. G. Carcajal, A CMOS transconductor with multidecade tuning using balanced cur rent scaling in moderate inversion, IEEE J. SolidState Circuits, vol. 40, no. 5, pp. 10781083, May 2005.

