Design of Low Voltage High Speed Operational Amplifier for Pipelined ADC in 90 nm Standard CMOS Process

DOI : 10.17577/IJERTV1IS4073

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Design of Low Voltage High Speed Operational Amplifier for Pipelined ADC in 90 nm Standard CMOS Process

Shri Kant

M.Tech. (VLSI student), Department of electronics and communication engineering NIT Kurukshetra, India

O. P. Sahu


Department of Electronics and communication engineering NIT Kurukshetra, India


This paper presents the low voltage high speed operational amplifier for pipelined ADC in 90nm standard CMOS process. The designed Opamp can operate at a supply voltage of 1V and provides a gain of 81.11 dB, unity gain frequency of 485.2MHz and slew rate of 239.62V/µs with 12ns settling time. The schematic is captured using Cadence Virtuoso and simulated using Cadence Spectre simulator in 90nm CMOS technology. The designed Opamp satisfies the requirements of a pipelined ADC and can be utilized in the S/H block of pipelined ADC.

  1. Introduction

    In the past few years, mobile phones have become a very common thing for every individual and the number of subscribers is increasing day by day which requires the base station of a cell to be very fast. Analog to digital converters are very basic part to any base station receiver .So high speed ADC architecture like pipelined ADC is used in UMTS base station receivers [1-3]. The most important part in a pipelined ADC is the operational amplifier which is used in Sample and Hold (S/H) circuit. In this paper, design of a high speed operational amplifier for pipelined ADC is presented which can provide a d.c. gain of 81.11dB, unity gain frequency of 485.2MHz, slew rate of 239.62V/µs and settling time of 12ns. The Speed of an operational amplifier is determined by the rate of change of output voltage with time. The change in output voltage occurs in two manners which are linear

    signal phenomenon which occurs when one of the input signals is much larger than the other. In this situation one of the input transistors turns off and the Opamp behaves as non-linear device and the output capacitor charges with a constant current [5].When the output decreases, the transistor turns ON and linear settling occurs. The Opamp used in S/H circuit of pipelined ADC also requires a very high gain so some sort of gain enhancement technique [6-7] is required which is discussed in section 3.

  2. Basic Opamp topologies

    A number of Opamp topologies exist in literature, each having its own advantages and disadvantages, some topologies have a very high gain but less swing and speed, some have well speed but the gain is not adequate, some topologies are a mixture of more than one basic topologies. So an appropriate blend of these topologies is required which can provide very high gain, swing, speed and UGF but less power dissipation. The different topologies are discussed in this section.

    1. Simple differential amplifier

      A simple differential amplifier is simply two single ended amplifiers which are given differential inputs and the differential output is taken. A tail current source provides a constant current to make the sum of two currents independent of the input common mode level. A fully differential configuration [8] provides a good swing as compared to single ended amplifier and supresses the supply noise. A simple differential amplifier is shown in Fig. 1.

      The gain of a simple differential amplifier is

      and non-linear settling (or slewing).Linear settling depends on Unity Gain Frequency and the non-linear settling depends on slew rate [4]. Slewing is a large



      The swing of differential amplifier is twice as compared to the swing of a simple common source amplifier.

      Vout = 2(Vdd – Vod3 – Vod1 – VIss)

      Fig. 1 Simple differential amplifier

    2. Telescopic amplifier

      A telescopic amplifier [9-11] is simply the extension of amplifier shown in Fig. 1 where the input and load transistors are replaced by cascode pairs so as to increase their output resistance which increases the gain of the amplifier given as

      Av=gm1 [(gm3.ro3.ro1) || (gm5.ro5.ro7)]

      The detailed schematic of telescopic amplifier is shown in Fig. 2.

      Fig. 2 Telescopic amplifier

      Besides its high gain, this topology is not used because of small voltage swing which is limited by the overdrive voltage of five cascode transistors. The

      minimum and maximum value of single ended swing is given by

      Vout, min = Vod1 + Vod3 + Vod9 Vout, max = Vdd – Vod5 – Vod7

      The overall swing at one end of output is given as the difference of maximum and minimum swings.

      Vout = Vout, max – Vout, min

    3. Folded cascode amplifier

      Folded cascode is used to increase the output swing of cascode amplifier. As shown in Fig. 3, this amplifier folds the input transistors to either Vdd or ground and two tail current sources are applied at the point of folding. The gain of this type of amplifier is slightly less than the gain of telescopic amplifier (ro1 comes in parallel with r05) but the swing is higher by the overdrive voltage of tail current source.

      Fig. 3 Folded Cascode amplifier The gain of folded cascode amplifier is

      Av= gm1 {[gm3.ro3. (ro1||ro5)] || [gm7.ro7.ro9]}

      The swing of folded cascode amplifier is higher than the swing of telescopic amplifier by the overdrive voltage of tail current source .The minimum and maximum values of single ended swing are

      Vout, min = Vod7 + Vod9

      Vout, max = Vdd – Vod3 – Vod5

    4. Two stage amplifier

      As a single stage telescopic amplifier can provide good gain but swing is less, a simple differential amplifier have good swing but less gain. So, the gain and swing requirements trade with each other [12] but a two stage amplifier can be designed in such a way

      that the gain and swing are independent. So the first stage can provide a high gain and second stage can provide a high swing and each can be controlled independent of each other. As shown in Fig. 4, first stage uses a telescopic amplifier which provides good gain while the second stage uses common source amplifier which consumes very less voltage headroom and hence provides a high output swing. The amplifier shown in Fig. 4 can be a combination of any of basic amplifier configurations e.g. it can be a simple differential amplifier or a folded cascode amplifier in first stage but the second stage is generally common source stage due to its high swing. Three stage amplifiers are also possible but rarely used because of speed limitations.

      Av= gm1 {[A2.gm3.ro3. (ro1||ro5)] || [A1.gm7.ro7.ro9]}

      Here A1 and A2 are the gain of lower and upper auxiliary amplifiers respectively.

      Fig. 5 Folded cascode amplifier with gain boosting

      The aspect ratios of all the transistors are shown in Table 1.

      TABLE I





      (W/L )3-4























      Fig. 4 Two stage amplifier

  3. Proposed Design technique

    1. Proposed design topology

      The proposed design topology uses a folded cascode amplifier for high speed and swing and the gain boosting technique to increase the gain. The auxiliary amplifiers used in Fig. 5 for gain boosting are simple differential amplifiers which enhances the output resistance of cascode transistor pairs M3,5 and M7,9 resulting an increase in overall gain of amplifier.

    2. Gain boosting

      Gain boosting is a technique to increase the gain of operational amplifiers using auxiliary amplifiers to increase the output impedance of cascode transistor pairs [13-14]. Because the gain of an amplifier depends directly on the output impedance, so the gain of the overall configuration increases. Fig. 5 illustrates the gain boosting technique applied to folded cascode differential amplifier.

  4. Simulation results

    The designed Opamp was simulated with Cadence Spectre simulator using 90nm CMOS technology. The aspect ratios of all the transistors are shown in Table 1.The gain and phase plot of Opamp are shown in Fig. 6, which exhibits a d.c. gain of 11362 i.e. 81.11dB which is sufficient enough for S/H circuit of pipelined ADC. It shows a unity gain bandwidth of 485.2MHz and the phase margin is 19.07 degrees.

    Fig. 6 Gain and phase plot of Opamp

    A transient analysis was performed with a unit step input of 0.4V applied at one end and -0.4 V at another end with a very small rise and fall time (1ps) and the differential output is plotted against time, the slope of which shows the rate of change of output with time i.e. slew rate of 239.62V/µs indicating a steep increase in the output with time for large signals. The differential output reaches 99% of its final value within 12ns indicating a fast settling as shown in Fig. 7.

    Fig. 7 Settling behaviour of Opamp

    The designed Opamp is applied with a common mode sinusoidal input signal of 10mV, 10MHz and the CM gain is plotted with frequency as shown in Fig. 8 which shows a common mode gain of 7.582X10-6 i.e. -102.4 dB.

    The CMRR can thus be calculated as CMRR=Av, diff/Av, CM

    The value of CMRR comes out to be 183.51dB.

    Fig. 8 CM gain as a function of frequency

    To calculate the PSRR, an a.c. signal of 10mV, 50Hz is superimposed on Vdd with no input applied at inverting and non-inverting terminals and the gain

    w.r.t. supply voltage (Av, PS) is plotted with frequency as shown in Fig. 9.The power supply gain is 3.94X 10-8

    i.e. -148.1dB.

    The PSRR is given by PSRR= Av, diff/Av, PS

    Fig. 9 Gain w.r.t. power supply plotted with frequency The simulation results are summarised in Table 2.





    Gain crossover frequency


    Phase margin


    Differential Output




    Slew Rate

    +239.62 V/µs

    -239.41 V/µs

    Settling time


    Power Dissipation

    73.72 µW







  5. Conclusion

    The designed Opamp achieved a gain of 81.11dB with a unity gain frequency of 485.20 MHz at a power supply voltage of 1V which meets the specifications of S/H circuit for a pipelined ADC. The designed Opamp achieved a high slew rate of +239.62V/µs and – 239.41V/µs and settling time of 12ns which is in accordance with our specifications of high speed ADC.However it suffers from a low phase margin which can lead to instability in closed loop configurations of Opamp.

  6. References

  1. Walt Kester, Which ADC Architecture Is Right for Your Application?, Analog Dialogue 39-06, June 2005

  2. Yen-Chuan Huang and Tai-Cheng Lee, A 10-bit 100- MS/s 4.5-mW Pipelined ADC with a Time-Sharing Technique, IEEE transactions on circuits and systems-II:

    Regular papers, Vol. 58, No. 6, June 2011

  3. Junhua Shen and Kinget P.R., A 0.5-V 8-bit 10-Ms/s Pipelined ADC in 90-nm CMOS, IEEE Journal of solid-state circuits, Vol. 43, issue 4, Apr. 2008

  4. Mohammad Yavari and Nima Maghari, An accurate analysis of slew rate for operational amplifier, IEEE transactions on circuits and systems-II: express briefs, vol. 52, no. 3, Mar. 2005

  5. Behzad Razavi, Design of analog CMOS integrated circuits, Tata McGraw-Hill Edition, 2002

  6. Mrinal Das, Improved design criteria of gain-boosted CMOS OTA with high-speed optimizations, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 49, No. 3, Mar. 2002

  7. Flandre, Alberto Viviani, Jean-Paul Eggermont Bernard Gentinne, and P. G. A. Jespers,, Improved synthesis of gain- boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology, IEEE Journal of solid-state circuits, VOL. 32, No. 7, July 1997

  8. J.J. Cooley, A.T. Avestruz and S.B. Leeb, Small-signal analysis of fully-differential closed-loop op-amp circuits with arbitrary external impedance elements, IET Circuits, Devices & Systems, Nov. 2010

  9. Jose-Angel Diaz-Madrid and Harald Neubauer Gines Domenech-Asensi and Ramon Ruiz, Comparative analysis of two operational amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35m CMOS, IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, June 2008

  10. Kush Gulati and Hae-Seung Lee, A High-Swing CMOS Telescopic Operational Amplifier , IEEE Journal of solid- state circuits, VOL. 33, No. 12, Dec. 1998

  11. David G. Nairn, Cascode Loads and Amplifier Settling Behaviour, IEEE Transactions on circuits and systems-I:

    Regular papers, Vol. 59, No. 1, Jan. 2012

  12. Salvatore Pennisi, Giuseppe Scotti, and Alessandro Trifiletti, Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers, IEEE transactions on circuits and systems-1: regular papers, vol. 58, No. 9, Sep. 2011

  13. Manas Kumar Hati and Tarun K. Bhattacharyya, Design of a low power, high speed complementary input folded regulated cascode OTA for a parallel pipeline ADC, IEEE Computer Society Annual Symposium on VLSI ,July 2011

  14. Haitao Wang, Hui Hong, Lingling Sun, and Zhiping Yu, A sample-and-hold circuit for 10-bit 100MS/s Pipelined ADC, IEEE 9th International Conference on ASIC (ASICON), Oct. 2011

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