 Open Access
 Total Downloads : 290
 Authors : Mohammed Sayeeduddin Habeeb, Mohd Salahuddin
 Paper ID : IJERTV5IS020152
 Volume & Issue : Volume 05, Issue 02 (February 2016)
 DOI : http://dx.doi.org/10.17577/IJERTV5IS020152
 Published (First Online): 11022016
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Design of Low Power SRAM using Hierarchical Divided Bitline Approach in 180nm Technology
Mohd. Sayeeduddin Habeeb #1, Md, Salahuddin #2
Lecturer Asst. Professor
King Khalid University Azad College of Engineering and Technology Saudi Arabia Hyderabad, India
Abstract Fast low power SRAMs have become a critical component of many VLSI chips. This is especially true for microprocessors, where the onchip cache sizes are growing with each generation to bridge the increasing divergence in the speeds of the processor and the main memory. Simultaneously, power dissipation has become an important consideration both due to the increased integration and operating speeds. Thus, a significant effort has been invested in reducing the power of CMOS RAM chips using circuit and architectural techniques. This paper presents a design using hierarchical divided bitline approach for reducing active power in SRAMs by 4050% and access time at the expense of 510% increase in the number of transistors when compared to Conventional SRAM. A Hierarchical divided bit line approach is chosen to implement a 1Kb SRAM memory on 0.18 micron CMOS technology using CADENCE design tool.
Keywords SRAM Cell, Power, Hierarchical divided bit line approach, bit line capacitance.

INTRODUCTION
Static random access memory (SRAM), being the fastest of the currently high volume manufactured memory families, continues to be a critical component for a multitude of electronic applications. Several techniques have been proposed to reduce the power consumption of SRAMs .The read power is reduced by limiting the swing voltages of bit lines and data bus to small voltages during read cycles. However, the SRAM consumes much larger power during write cycles than read cycles due to the full swing property in the bit lines and data bus during write cycles. If the same voltage swing is allowed, then power consumed during read or write is directly proportional to the capacitance of bitline. Bitline capacitance can be reduced by the proposed divided bitline approach, where the number of transistors connected to the bitline is reduced by combining two or more SRAM cells. Combination of two or more SRAM cells results in division of bitline into several sub bit lines. These sub bit lines are further combined to obtain two or more levels of hierarchy The basic idea behind this extension is to make use of these sub bitlines, which have much smaller capacitance, to develop a limited voltage swing on the bitline. This division of bitline into hierarchical sub bitlines results in reduction of bitline capacitance, which reduces active power.

SRAM CELL
Memory cells are the key components of any SRAM unit. An SRAM cell can store one bit of data. An SRAM cell comprises two backtoback connected inverters forming a latch and two access transistors. Access transistors serve for read and write access to the cell.
An SRAM cell offers the following basic properties. [3]

The data read operation should not destroy the stored information in the SRAM cell.

The cell should allow modification of the stored information during the data write phase.
Read Operation
Consider the data read operation first, assuming that logic "0" is stored in the cell. The voltage levels in the CMOS SRAM cell at the beginning of the "read" operation are depicted in Figure 1. Here, the transistors M2 and M5 are turned off, while the transistors Ml and M6 operate in the linear mode. Thus, the internal node voltages are V1 = 0 and V2 = VDD before the cell access (or pass) transistors M3 and M4 are turned on. The active transistors at the beginning of the dataread operation are highlighted in Figure 1.
Figure 1 Voltage levels in the SRAM cell at the beginning of the "read" operation
After the pass transistors M3 and M4 are turned on by the row selection circuitry, the voltage level of column C will not show any significant variation since no current will flow through M4. On the other half of the cell, however, M3 and Ml will conduct a nonzero current and the voltage level of column C will begin to drop slightly. The voltage difference is fed to sense amplifier.
Write Operation
Consider the write "0" operation, assuming that logic "1" is stored in the SRAM cell initially. Figure 2 shows the voltage levels in the CMOS SRAM cell at the beginning of the data write operation. The transistors M1 and M6 are turned off, while the transistors M2 and M5 operate in the linear mode. Thus, the internal node voltages are V = VDD and V2= 0 V before the cell access (or pass) transistors M3 and M4 are turned on.
0v Vdd
Figure 2 Voltage levels in the SRAM cell at the beginning of the "write" operation.
The column voltage VC is forced to logic "0" level by the datawrite circuitry; thus, it may be assumed that VC is approximately equal to 0 V. Once the pass transistors M3 and M4 are turned on by the row selection circuitry, we expect that the node voltage V2 remains below the threshold voltage of Ml. Consequently, the voltage level at node 2 would not be sufficient to turn on Ml. To change the stored information, i.e., to force V, to 0 V and V2 to VDD, the node voltage V1, must be reduced below the threshold voltage of M2, so that M2 turns off first. Note that a symmetrical condition also dictates the aspect ratios of M6 and M4.


CONVENTIONAL SRAM
The Figure 3 illustrates the Conventional SRAM memory design consisting of array of SRAM memory cells.
Figure 3 Conventional SRAM Memory Design
In a read operation, the bit lines start pre charged to some reference voltage usually close to the positive supply. When word line turns high, the access transistors connected to the cell node storing a 0 starts discharging the bit line, while the complementary bit line remains in its pre charged state, thus resulting in a differential voltage being developed across the bit line pair. SRAM cells are optimized to minimize the cell area, and hence their cell currents are very small, resulting in a slow bit line discharge rate. To speed up the RAM access, sense amplifiers are used to amplify the small bit line signal and eventually drive it to the external world During a write operation, the write data is transferred to the desired columns by driving the data onto the bit line pairs by grounding either
the bit line or its complement. If the cell data is different from the write data, then the 1 node is discharged when the access transistor connects it to the discharged bit line, thus causing the cell to be written with the bit line value.
IV HIERARCHICAL DIVIDED BIT LINE APPROACH
Divided BitLine Approach
Power consumption in SRAMs, for a normal read cycle, is given by the below expression
P = Vdd Ã— Idd (1)
Idd = (mIactt + C pt Vint) f + Idcp (2) where, Vdd is an external supply voltage, Idd is the total current, I act is the effective active current, Vint is an internal supply voltage, CPT is the total capacitance of the peripheral circuits, Idcp is the total static current, m is the number of columns and f is the operation frequency. This equation is based on the fact that in SRAMs, holding current is very small and decoder charging current is negligible because of NAND decoders. To reduce the total power consumption, active current should be reduced as it dominates the total current. Active current is the current that flows during word line activation, i.e., during charging or discharging of bitline capacitance. Ths active current is directly proportional to bit line capacitance [6].
Here the approach presented reduces Idd by reducing the active current, I act .The total effective charging current owing through a bitline, during a read operation, can be expressed as
Ieff = Ceff Ã— V/T (3) where Ceff is the effective bitline capacitance, V is the voltage swing and T is the word line activation time. Similarly, expression for power can be written
P= (Ieff Ã—V Ã—T) Ã—f (4)
The bitline capacitance is mainly composed of the drain capacitance of the pass transistors of the SRAM cell and metal capacitance of bitline.
Figure 4 Divided Bit Line Approach
To reduce this capacitance, drain capacitance and metal capacitance should be reduced.
Theoretical Basis
In this subsection, we provide a theoretical basis for our approach and derive an optimal value for the number of SRAM cells to be combined [16].
Figure 5 RC model for Pass transistors reading 1 stored in SRAM cell
Figure 5 shows the modeling of passtransistors as RC chain. As bitlines are always precharge before reading, analysis is performed for bit line (or bitline) which has to be pulled down to read a `1' (or a `0'). The access time Delay can be written in terms of parameters TP, TD2 and TR2 as
Td2 – Tr2 + Tr2 ln {Tr2/Tp[V(t)]} Tdelay Tp – Tr2
+ ln {Td2/Tp[v(t)]} (5)
Where V (t) is the normalized voltage with respect to supply and is given by 1(V/v).
The parameters TP, TD2, TR2 are given by following equations are obtained from Elmore delay model
T p = Td2 = R1C1+ (R1 + R2) C2 (6)
2
2
Tr2 =R1 C1/ (R1 + R2) C2+ (R1+R2) C1 (7)
Where R1 is the resistance of the passtransistor 1 and R2 is the resistance of the passtransistor 2. C1 and C2 are the capacitances at node 1 and at node 2, respectively, in above Fig 5.
Let us assume that the number of rows in the memory array is N and the number of cells combined in the divided bitline is denoted by M. Then, the capacitances C1 and C2 can be obtained as
C1 = C (M + 1)/N (8)
For N 1; C = C (M)/N (9)
C2 =C/M+ 0.1 Ã—C (10)
where C denotes the original drain capacitance of N rows. Metal capacitance contribution to total bitline capacitance is assumed to be 10% of the total drain capacitance. To make a first order approximation, the resistances of two pass transistors are assumed to be equal. From the above equations and assumptions the delay is found as
T delay = RC {M/N + 2/M +0.2} Ã— ln (1/V (t)) (11)
Using this approximated delay we can write normalized delay as
T delay (normalized) =1/1.1Ã— [(M/N) + (2/M) +0.2] (12)
Now, an optimal value of M for minimum power consumption is found. The optimal Value for number of cells to be combined is given by differentiating (12) w.r.t M.
Where N is number of rows, v is voltage swing.
M optimal= [(N/2) Ã— (V/v)] (13)
Power consumption, as a function of N and M, can be expressed as
Power = f (M) = {C2Ã—vÃ—V+2Ã—C1Ã—V2) Ã—f
=[{C/M+0.1Ã—C}Ã—vÃ—V+2Ã—C(M/N)Ã—V2]Ã—f (14)
Hierarchical Divided BitLine Approach
In high density SRAMs, the number of sub bit lines will increase and even with divided bitline architecture, bitline capacitance can be significant. From this point of view, hierarchical divided bitline architecture is developed [2]. Figure. 6 shows the concept of hierarchical divided bitline approach.
In this architecture, the bit line is divided into more than two levels. Let us assume that the total number of levels in the hierarchy is L and at each level I, the number of blocks combined to form a new block is Mi [5]. Then capacitance, C i at each node is given by
C I = C (Mi+1)/N (15)
CL = C Ã— 1/( I =1 L1) (16)
Using these capacitances and again making the assumption that resistance values of all pass transistors are equal, the expression for active power can be written as
Power = f (M1, .ML1; L)
= 2V2C/N Ã— i=1 Mi + CVV/ Mi + 0.1 CVV (17)
Similarly the expression for delay of hierarchical bit line can be written as
T delay = RC Ã— L1i=1 [M I /N] + L /( I =1 L1 M I ) + 0.1 Ã— L (18)
Figure 6 Hierarchical divided bit Line Approach
To obtain the optimum parameter for the number of blocks combined at each level, we differentiate (16) partially with respect to all Mi's and solve the following equation
f/Mi = 0 for i1 to L1 (19) The solution to the above equation gives the optimum values for Mi's, which are given by
M1=M2=…=ML1= (N/2Ã— v/v) 1/L (20)
By substituting these values for Mi's expression for Power is obtained as
Power= (2V2C/N) LÃ— (N/2Ã—v/v) 1/L (21)
V PERFORMANCE ANALYSIS
The power consumption for the SRAM memory design using various approaches is compared in this section. The Figure 7 illustrates the power consumption during write operation for 64bit SRAM memory design using DBL and HDBL.
Figure 7 Power consumption SRAM memory (64bit)
The power consumed during the write operation is measured in w. The DBL approach saves approximately 35% of power when compared to CVSRAM memory design. The HDBL saves around 46% of power during write operation. The Figure 8 illustrates the power consumption during both read/write operation for 1KB SRAM memory design using various approaches. The power consumed is measured in w.
Figure 8 Power consumption Memory design (1KB)
Bit Line Capacitance Analysis
Bit line capacitance is the major concern for power consumption in SRAM.
In general the drain capacitance Cdrain = 0.5fF1fF, Wire capacitance, Cwire = 0.2fF/micron of wire. The bit line capacitance in general is given by
C bit = (source/drain cap + wire cap + contact cap) x no. of cells in column

For Conventional SRAM the bit line capacitance is as shown below
Bit line capacitance/column = 16fF Total bit line capacitance = 512fF

For divided bit line approach the capacitance across bit line is divided as C1 and C2 where
C1 = C (M/N) and C2 = [C/M] +) 0.1C
Where N= number of rows, M= no of cells combined and C= original drain capacitance.
Bit line capacitance /Column is given by = 10.56fF Total bit line capacitance = 337.92fF.

For hierarchical divided bit line approach the capacitance Ci indicates the capacitance at each node i, and CL indicates capacitance at each level given by
Ci = C [Mi/N] Where N=number of rows and Mi = No of cells combined
Bit line capacitance/Column = 8.0624fF, Total bit line capacitance = 257.99fF.
Bit line Capacitance Comparison
Approaches 
SRAM 
DBL 
HDBL 
Bitline capacitance/column 
16fF 
10.56fF 
8.0624fF 
Total bit line capacitance 
512fF 
337.92fF 
257.99fF 
This illustrates the reduction in the value of capacitance in DBL and HDBL approach when compared to conventional SRAM.
VI SIMULATION RESULTS
SRAM Cell
The Schematic entry and layout of the propose hierarchical divided bit line approach is done using Cadence tool on 180nm. Figure 9 shows the SRAM cell schematic entry. The design of the cell involves the selection of transistor sizes for all six transistors to guarantee proper read and write operations.
Figure 9 SRAM Cell Schematic Entry
The Figure 10 illustrates the Layout view of the 6T CMOS SRAM cell. The area of the SRAM cell is 14 m. The power consumed is 6.426w.
Figure 10 SRAM Cell Layout
The Figure 11 illustrates the simulation results of the SRAM cell.
Figure 11 SRAM Cell Simulation Result
Sense Amplifier Circuit
The sense amplifier used is the latch based sense amplifier shown in figure 5.3(a). The sense amplifier circuit consists of Sense enable signal which i enabled during read operation. The output consists of Out and Out bar pins in order to access the data from the cell selected with the help of decoder circuits.
Figure 12 Sense Amplifier Schematic
The Figure 13 illustrated the layout sketch of the sense amplifier circuit schematic. The area of the Sense amplifier circuit is 1.5 m. The power consumption is 99.01w. The Figure 14 illustrates the simulated results of the sense amplifier circuit for which the schematic and layout sketch shown . The X axis is labeled as Timens. The Y axis consists of the parameters sense enable (SE) signal, Out, out bar.
Write Driver Circuit
Simplified write circuitry for the SRAM memory operation is shown below in Figure 15. The input signal is viewed only when the write enable signal is enabled.
Figure 13 Sense Amplifier Layout
Figure 14 Sense Amplifier Simulated Waveform
Figure 15 Write Driver Circuit Layout
Conventional SRAM memory design (1Kb)
The Figure 16 illustrates the layout sketch for SRAM memory design of 1Kb.The area consumed by the memory design is around 3085m.the power consumption during write operation is 884.7w.
Figure 16 CV SRAM Memory design layout 1Kb
Memory design using divided bit line approach (1Kb)
The Figure 17 illustrates the memory design of 1Kb using divided bit line approach. The area consumed by the memory design using divided bit line approach is around 3784m.The power consumption during write operation is 460.26w.
Figure 17 SRAM memory using divided bit line approach layout sketch 1KB
Memory design using hierarchical divided bit line approach (1Kb)
The Figure 18 illustrates the memory design of 1Kb using HDBL approach. The Figure 19 illustrates memory design using Hierarchical divided bit line approach layout sketch 1Kb.The area consumed by the memory design using hierarchical divided bit line approach is 4715m.The power consumed during write operation is 354w.
Figure 18 SRAM memory using Hierarchical divided bit line approach 1Kb
Figure 20 SRAM memory write operation using Hierarchical divided bit line approach 1Kb
Figure 21 SRAM memory read operation using Hierarchical divided bit line approach 1Kb
VII CONCLUSION
This paper presents a 6Tbased SRAM memory, and the various design techniques used to overcome power dissipation factor. A basic 6T SRAM structure is chosen for designing the SRAM bit cell which is used further for memory design, after this low power design techniques such as divided bit line and hierarchical divided bit line approach are implemented on the SRAM memory design. The conventional SRAM (CVSRAM) and SRAM using Hierarchical divided Bit line Approach is implemented for the comparisons. The architecture of the CV SRAM is almost the same as that of the other HDBL – SRAM except that the CVSRAM uses the conventional bit line whereas the other SRAM uses the hierarchical bit line. Using this approach the power consumption is reduced at the expense of slight increase in the number of transistors when compared to Conventional SRAM. Thus the power consumed is decreased by 5060% using HDBL and 3040% using DBL successfully. The area consumed by the memory design of 1Kb is around 3085Âµm and for the memory design using divided bit line approach area consumed is around 3284 Âµm and for memory design using hierarchical divided bit line approach it is 3615Âµm. Thus the memory design using SRAM cell is implemented by various approaches for reducing power around 5060% at the expense of 1020% increase in area.
Figure 19 SRAM memory using Hierarchical divided bit line approach layout sketch 1Kb
The Figure 20 and Figure 21 illustrates the write and read operation of memory 1Kb using HDBL.
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AUTHORS PROFILE:
Mr. Mohammed Sayeeduddin Habeeb completed his Masters of Engineering specializing in Communication Engineering from Osmania Univesity, India. He completed his research thesis at DOFI, RCI, DRDO laboratory (Ministry of Defence) and designed Programmable Pre Modulation Filter in Avionic application. After completing his Masters studies he worked as
Asst. Professor at Shadan College Of Engineering and Technology, India. Since 2012 he is working as a lecturer in King Khalid University, Abha. His research interests are Design and analysis of digital filters, digital signal processing and there optimization methods
MD SALAHUDDIN received the B.Eng. in Electronics and Communication Engineering from Osmania University, Hyderabad, AP, INDIA in 2010, and the M.Tech. in VLSI System Design from JNT University, Hyderabad, TS, INDIA in 2012. His research interests include Wireless Communication, Microelectronics, Analog VLSI, Image processing, Embedded Systems.
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