Design of Low Power Resistive Random Access Memory using Memristor

Design of Low Power Resistive Random Access Memory using Memristor

Thangamani.V

Department of ECE, PG Student Kalaignar Karunanidhi Institute of Technology

Abstract

The computer memory system has both volatile and non volatile memory. The Volatile memories such as SRAM and DRAM used as a main memory and non volatile memory like flash memory. But in recent days new non volatile technologies are invented that promise the rapid changes in the landscape of memory systems. Memristor is a two terminal passive element whose resistance depends on the magnitude and polarity of the voltage applied to it. It has nonlinear relationship between voltages and current which is similar to memory devices. In this paper we approach to design memristor based nonvolatile 6-T static random access memory (SRAM) and analysis the circuit performance with conventional 6-T SRAM cell in order to prove the parameter optimizations. Then we address the memristor-based resistive random access memory (MRRAM) which is similar to that of static random access memory (SRAM) cell and we compare the nonvolatile characteristics of MRRAM with SRAM cell.

Index terms: NV memory, memristor, SRAM, Resistive RAM, SPICE model.

1. Introduction

   Leon Chua [1] envisioned the fourth non-linear passive two terminal electrical component called memristor in 1971. It relates electric charge and magnetic flux linkage for a particular time interval. In 2008, researchers at Hewlett Packard (HP) Labs reported that the memristor was realized physically using thin film of titanium dioxide nanoscale device [2]. Basically the memristor is a resistance with memory. Its resistance chances when a voltage is applied to this element and remains constant on that particular value when the applied voltage is removed. The main difference between the memristor (M) and the three passive elements (R, L, C) is its nonlinear input-output characteristics. Memristors are also used as programmable resistive loads in a differential

   amplifier [7]. Memristor act as a strong candidate for future memories because of its non-volatile property and high packing density in a crossbar array [11]. The main feature of our circuit is its non-volatility and its reduced size compared to the conventional 6T-SRAM. The data is retained in the memory even when the power is turned off for an indefinite time. The area can be much less than the conventional SRAM cells since each memory cell consists of only three transistors and two memristors.

   Resistive RAM is a device that can switch between one or more resistances under the application of appropriate voltages. It shows memristive behavior, and can be thought of as a specific type of memristor. Devices can have two or more discrete resistance states, or may have a continuously variable resistance. Whatever the case, it is important that the change in resistance is governed by the past history of the device that is, by the previous voltage applied, or the previous current that has flowed through the device. RRAM devices may help overcome some of the bottlenecks that we are currently facing in microelectronics.

   The paper starts off with the introduction of memristor and its characteristics. After that some related works and the structure of the memristor based SRAM circuit, its working principle and the functionality. Then it discusses the perspectives, draws some comparisons and finally it concludes with the prospects of memristive based resistive RAM circuit.

2. Memristor characterization

   The memristor was defined in terms of a non-linear functional relationship between the magnetic flux m(t) and the amount of electric charge that has flowed q(t), as

   f(m(t),q(t)) = 0

   The variable m ("magnetic flux) is generalized from the circuit characteristic of an inductor. It does not represent a magnetic field here. Its physical meaning is discussed below. The symbol m may be regarded as the integral of voltage over time [20].

   In the relationship between m and q, the derivative of one with respect to the other depends on the value of one or the other, and so each memristor is characterized by its memristance function describing the charge-dependent rate of change of flux with charge.

   M(q) =

   Substituting the flux as the time integral of the voltage, and charge as the time integral of current, the more convenient form is

   M(q(t)) = =

   To relate the memristor to the resistor, capacitor, and inductor, it is helpful to isolate the term M(q), which characterizes the device, and write it as a differential equation.

   Figure 1. Relationship between three basic components and memristor

   The above figure covers all meaningful relationships of I, Q, m, and V. No device can relate dI to dq, or dm to dV, because I is the derivative of Q and m is the integral of V. It can be inferred from this that memristance is charge-dependent resistance. If M(q(t)) is a constant, then we obtain Ohms Law R(t) = V(t)/ I(t). If M(q(t)) is nontrivial, however, the equation is not equivalent because q(t) and M(q(t)) can vary with time. Solving for voltage as a function of time produces the following equation,

   V(t) = M(q(t))I(t)

   This equation shows that memristance defines a linear relationship between current and voltage, as long as M does not vary with charge. Nonzero current implies time varying charge. Alternating current, however,

   may define the linear dependence in circuit operation by inducing a measurable voltage without net charge movementas long as the maximum change in q does not cause much change in M. Furthermore, the memristor is static if no current is applied. If I(t) = 0, we find V(t) = 0 and M(t) is constant. This is the essence of the memory effect. The power consumption characteristic recalls that of a resistor, I2R.

   P(t) = I(t)V(t) = I2(t)M(q(t))

   As long as M(q(t)) varies little, such as under alternating current, the memristor will appear as a constant resistor. If M(q(t)) increases rapidly, however, current and power consumption will quickly stop. M(q) is physically restricted to be positive for all values of q (assuming the device is passive and does not become superconductive at some q). A negative value would mean that it would perpetually supply energy when operated with alternating current. In 2008 researchers from HP Labs introduced a model for a memristance function based on thin films of titanium

   dioxide.[14] For RON<<ROFF the memristance function was determined to be

   M q(t)) = ROFF . (1 – q(t))

   Where ROFF represents the high resistance state, RON represents the low resistance state, v represents the mobility of dopants in the thin film, and D represents the film thickness. The HP Labs group noted that "window functions" were necessary to compensate for differences between experimental measurements and their memristor model due to nonlinear ionic drift and boundary effects.

3. Memristor as a switch

   For some memristors, applied current or voltage causes substantial change in resistance. Such devices may be characterized as switches by investigating the time and energy that must be spent to achieve a desired change in resistance. This assumes that the applied voltage remains constant. Solving for energy dissipation during a single switching event reveals that for a memristor to switch from Ron to Roff in time Ton to Toff, the charge must change by Q = QonQoff.

   Eswitch = V2

   2 2

   2 2

   = V = V

   =VQ

   Substituting V=I(q)M(q), and then dq/V = Q/V for constant VTo produces the final expressin. This power characteristic differs fundamentally from that of a metal oxide semiconductor transistor, which is capacitor-based. Unlike the transistor, the final state of the memristor in terms of charge does not depend on bias voltage.

   (a)

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   The type of memristor described by Williams ceases to be ideal after switching over its entire resistance range, creating hysteresis, also called the hard-switching regime [14]. Another kind of switch would have a cyclic M(q) so that each off-on event would be followed by an on-off event under constant bias. Such a device would act as a memristor under all conditions, but would be less practical.

4. Working principle of memristor

   Srrukov et al. [2] introduced a physical model of the memristor. They have shown that the memristor can be characterized by an equivalent time-dependent resistor whose value at a time t is linearly proportional the quantity of charge q that has passed through it.

   The HP device memristor is composed of a 50nm thin film of titanium dioxide sandwiched between two 5 nm thick electrodes, one titanium and the other platinum. Initially, there are two layers to the titanium dioxide film, one of which has a slight depletion of oxygen atoms. The oxygen vacancies act as charge carriers, meaning that the depleted layer has a much lower resistance than the non-depleted layer. When an electric field is applied, the oxygen vacancies drift (see Fast ion conductor), changing the boundary between the high-resistance and low-resistance layers. Thus the resistance of the film as a whole is dependent on how much charge has been passed through it in a particular direction, which is reversible by changing the direction of current [14].

   Since the HP device displays fast ion conduction at nanoscale, it is considered a nanoionic device [5]. The resistance change is non-volatile hence the cell acts as a memory element. Fig. 2(a) shows the doped and undoped region of a memristor.

   (b)

   Figure 2. (a) Characterizing the memristor and (b) Change of resistance when a 3.6V p-p square wave is applied.

   If a voltage is applied across the memristor,

   v(t) = M(t)i(t)

   M(t) = + ROFF (1- )

   Where RON is the resistance of completely doped memristor and ROFF is the resistance of completely undoped memristor, w(t) is given by

   i(t)

   µv is the average dopant mobility and D is the length of the memristor. From these equations, the considered nonlinearity produced from the edge of the thin film can be obtained as

   f() = – 1)2p .

   Change of resistance of a memristor applying 3.6 V p- p square wave across it is shown in Fig. 2(b). Resistance of the memristor changes from 20K to 100 in positive cycle and this change occurs in reverse direction when the square pulse reverses its direction.

5. Related works

   Static random-access memory (SRAM) is a type of semiconductor memory that uses bistable latching circuitry to store each bit. The term static differentiates it from dynamic RAM (DRAM) which must be periodically refreshed. SRAM exhibits data remanence[1], but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered. The operation of SRAM cell has three different states. It can be in: standby (the circuit is idle), reading (the data has been requested) and writing (updating the contents). The SRAM to operate

   in read mode and write mode should have "readability" and "write stability" respectively.

   The most commonly used SRAM type is the 6T SRAM which offers better electrical performances from all aspects (speed, noise immunity, standby current). The smallest 6T-SRAM cell that has been fabricated till today has an area of 0.08µm2 and itwas fabricated in the 22 nm process using immersion and EUV lithography [15]. The main disadvantages of the 6T SRAM structure are its large size and high power consumption. To overcome these limitations, memristive-RAMs are being developed recently. According to HP, resistive random access memory (ReRAMs), which are memristor-based versions of both DRAM and SRAM, ought to speed up computers immensely. In [16], a complementary resistive switch was introduced which consisted of two anti-serial memristive elements which validates the construction of large crossbar arrays with a reduced power consumption.

6. Memristor based SRAM

   Electrical scheme of the proposed SRAM cell is shown in Fig. 3(a). Two memristors are acted as memory element. The arrangement is in such a way that during write cycle, they are connected in parallel but in opposite polarity [Fig. 2(b)] and during read cycle, they are connected in series [Fig. 2(c)].These connections are recognized by two NMOS pass transistors T1 and T2. A third transistor T3 is used to isolate a cell from other cells of the memory array during read and write operations. The gate input of T3 is the Comb signal which is the OR of RD (Read) and WR (Write) signals. RD is set to the LOW state and WR and Comb are set to the HIGH state for write operation. As a result, circuit of Fig. 3(b) is formed. The voltage across the memristors here is (VD- VDD/4). Depending on the data, it can be either positive (VD= VDD) or negative (VD= 0 V). Since the polarities of the memristors are opposite, change of memristances (or resistances) will also occur in the opposite direction. Now RD and Comb are kept in the HIGH state and this forms the circuit shown in Fig. 3(c).

   Voltage at D is now:

   VD = – ) × +

   Where, R1 and R2 are the resistances of M1 and M2 respectively. If 1 was written during write cycle, R2 becomes significantly greater than R1 and then VD is greater than VDD=4.

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   (a)

   (b) (c)

   Figure 3. (a) Three transistor-two memristor SRAM cell

   (b) Circuit when rd=0, wr=1, and Comb =1. (c) Circuit when rd=1, wr=0, and Comb=1.

   If 0 was written, R1 becomes significantly greater than R2 which makes VD to be as close as VDD=4. A comparator can be used as a sense amplifier to interpret these voltages as HIGH or LOW correctly.

7. Simulations

   A 16 x 16 array is considered for the verification of array structure of the NVRAM cell. Data is given through word lines/bit lines and switching is controlled by the Vdt and Vdtb signals. In the simulations data was written and read to calculate several important factors such as write time, read time, power consumption etc. A comparator is used as a sense amplifier to interpret these voltages as perfect

   1 and 0 and the reference of this should be tied to 0.26V. Simulation results are based on the following parameters:

   RON = 100, ROFF = 20k, p=10, D=3nm and µv =

   350×10-9 m2/s/V.

   1. Write operation

      In the first write cycle, 1 was written to cell2. Vwr2,Vrow0 and Vdt0 were set to HIGH state to select this cell. Timing diagram in Fig. 4(a) shows Vwr2, Vdt0 pulses and also shows the data in d0 which is Vwd0. This write cycle starts from 40 ns and during this cycle, Vwr2=1, Vdt0=1 and Vwd0=1. In the next cycle, a 0 was written to cell18 (from 50 ns) and to do this, Vwr2, Vrow1, Vdt1 were set to HIGH state and Vwd1 was set to LOW state.

      7. Perspectives

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      (a)

      (b)

      Figure 4. (a) Timing diagram of input pulses during write operation. (b) Change of resistance of the two memristors of cell20 during write operation.

      Finally a 1 was written to cell20 (from 60 ns). For this, Vwr4, Vrow1,Vdt1 and Vwd1, all were set to HIGH state. In Fig. 4(b), plot of the resistance of two memristors in cell20 shows the alteration of resistance while writing 1 into it.

   2. Read operation

After writing 1 in cell 2, the stored data was read (from 48 ns). For this, Vrd2 was set to HIGH state and data at dn0 is checked. In Fig. 5, timing diagram of read cycles is shown. After writing 1 in cell 18, all the powe sources are turned off during the time interval 50-69 ns. A read operation is done after turning on the power sources and found 1 in cell 18. During read operation at cell2, dn0 was found HIGH. Then after two write cycles, cell20 was read (from 68 ns) and found HIGH at dn1. Finally, cell18 was read (from 69 ns) and found LOW at dn1. So after reading a cell, data was found to be exactly the same as it was written previously in that cell. Thus, the array structure shows proper functionality both in read and write operations.

Figure 5. Evidence of non-volatility of the memristor SRAM cell.

Our proposed memristor based memory cell is non- volatile in nature. After writing 1 in cell 18, all the power sources were turned off during the time interval 50-69 ns (Fig. 5). A read operation is done after turning on the power sources and found 1 in cell 18. This proves the non-volatile nature of the cell. The write and read times were measured and compared in Table 1. The proposed NVRAM cell requires a bit more time for the write cycle than the conventional SRAM cells. By further increasing the mobility of the memristors, the write cycle time can be considerably reduced.

Table 1. Write/read time comparison.

Fig. 6 shows the inverse relation between mobility of the memristor and the write cycle time. The read cycle time depends on the sensitivity and responsiveness of the sense amplifier.

From simulation the power dissipation curve was found and integration was done to get the energy dissipated for separate operations (writing and reading 1 & 0). And then

the energy values were divided by respective operation cycle times to get the corresponding power dissipations (Table 2).The obtained values were then averaged to get the total power dissipation. This was compared with the value of the conventional SRAM cell in Table 3. Power consumption is much less than 6-T cell which can be reduced more by designing a faster comparator which would 99 reduce the read time. The area of the proposed memory cell can be predicted to be much less than the area of conventional 6-T SRAM cell,as only three transistors are used along with two memristors.

As memristors can be as small as 3 nm, the area can be further reduced if we can switch to more recent fabrication technologies such as 22 nm technology.

Table 2. Power dissipation during different operations

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Table 3. Power comparison

Figure 6. Inverse relation between mobility of the memristor and the write cycle time.

VII.CONCLUSION

In this paper, we intended a new idea of NVRAM cell using memristor. The read time is much faster compared to a conventional SRAM and the power consumption is also much smaller. However the writing speed is not satisfactory compared to existing SRAM cells due to the low mobility of the memristor in the SPICE model we used. Recent researches suggest that the write time can be significantly reduced [14], [20] using state-of-the-art fabrication techniques and also by using memristor based RRAM. There are further scopes to work on power consumption as well. Overall, it can be said that our proposed memristor based RRAM is a combination of new technology and innovative design which can open a new door in the field of memory design.

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