Design of Low Power, High Speed ADC by using Submicron Technology

DOI : 10.17577/IJERTV3IS20452

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Design of Low Power, High Speed ADC by using Submicron Technology

Ms. Kiran P. Kokate1, Prof. A. O. Vyas2

1ME. student, Electronics & Telecommunication Engineering, G.H. Raisoni College of Engineering & Management, 2Assit. Professor, Electronics & Telecommunication Engineering, G.H. Raisoni College of Engineering & Management, Amravati, (M.S.)


Abstract In modern era, VLSI design is one of the paradigms to have high speed, less power consumption, effective use of space, easily available productivity and mobility. Low power high speeds ADC can be design using VLSI.ADCs are key design blocks in modern microelectronic digital communication systems. With the fast advancement of CMOS technology, more & more signal processing functions are implemented in the digital domain for low cost, low power consumption, higher yield, & higher reconfigurability. Various example of ADC application can be found in data acquisition systems, measurement systems, digital communication systems also imaging, instrumentation systems. So, the proposed work is to design ADC in 90nm CMOS process.

The proposed work is to design and implement a successive approximation register (SAR) analog to digital converter (ADC) for communication domain. Sample and Hold circuit, Comparator are the basic building blocks of SAR ADC. The efficient design of Sample and Hold circuit and Comparator is drawn by using DSCH 3.5 software. Then, CMOS layout and simulation is drawn by using Microwind 3.1 software.


    An Analog-to-Digital Converter (ADC) is a device that converts a continuous physical quantity (usually voltage) to a digital number that represents the quantity's amplitude.

    The conversion involves quantization of the input, so it necessarily introduces a small amount of error. Instead of doing a single conversion, an ADC often performs the conversions ("samples" the input) periodically. The result is a sequence of digital values that have converted a continuous- time and continuous-amplitude analog signal to a discrete-time and discrete-amplitude digital signal.

    sampling. The electronic filter placed after a DAC is called reconstruction filter. It also eliminates the frequency above the Nyquist rate.

    In this, a brief overview of SAR ADC is provided to be effectively used in communication domain. Basically the objective of this project is to design the high speed ADC and which consume low power. So, the proposed work is to design such type of ADC.i.e.SAR ADC with high speed and low power consumption.


    In [1] A 10-bit SAR ADC for biomedical application was presented. The proposed SAR ADC achieves rail-to-rail input range and low power consumption. A Digital-to-Analog Converter (DAC) using C-2C capacitor array and dynamic comparator was used for low power consumption. It was realized in 0.18um standard CMOS technology. In [2] the design and implementation of 4-bit time interleaved SAR ADC for UWB application. Major contribution was that they use two capacitive DAC instead of three capacitive DACs. They implemented the ADC in 0.18m CMOS technology and had total power consumption of 23.3mw.In [3] SAR ADC implemented in a conventional 0.18um CMOS technology with low voltage. The SAR composite of sample-and-hold dummy switch compensation was employed, comparator is low voltage latched and realized based on current-mode approach, control logic circuit and digital to analog conversion consists of binary weighted capacitor arrays for differential inputs. In [5] A 10-bit dual-channel pipelined flash-successive approximation register (SAR) analog-to-digital converter (ADC) for high speed application was presented. The prototype ADC fabricated in a 45-nm CMOS process occupies

      1. mm2.


        1. SAR ADC

          Fig.1.1: Analog to Digital Converter

          The electronic filter placed before an ADC is called antialias filter. It is used to remove the frequency components above one half of the sampling rate that would alias during the

          In SAR ADC, it sets MSB. Then convert MSB to the corresponding analog output by using DAC. Then guess output will compare with the input. If Vin >1/2 ADC then it set the bit otherwise test the next bit. SAR ADC is capable of high speed and high resolution. They have low power consumption and low cost. They have medium accuracy and

          good tradeoff between speed & cost. They have no pipeline delay.

          Basically, the successive-approximation A/D converter consists of three main components an analog comparator, a DAC, and a successive-approximation register (SAR) all of which are connected in a feedback arrangement shown in Fig.3.1.

          Fig.3.3: CMOS layout of Sample and Hold Circuit

        2. Sample and Hold Circuit

          Fig.3.1: SAR ADC

        3. Comparator

          Comparator is the only analog block of a SAR ADC and performs the actual conversion. It compares the analog sampled input to the analog output of the DAC and generates digital output of 0 or 1 which will be used in the SAR logic. Accuracy and speed of the comparator are two important factors. The requirements of the comparator are speed and accuracy.

          In general, Sample and hold circuit (SHC) contains a switch and a capacitor. In the tracking mode, when the sampling signal is high and the switch is connected, it tracks the analog input signal. Then, it holds the value when the sampling signal turns to low in the hold mode.

          Sample and hold circuit (SHC) mainly used in ADC. It samples analog input signal & holds value between clock cycles. Stable input is required in many ADC topologies, which is provided by sample and hold circuit. it reduces ADC- error caused by internal ADC delay variations. Sometimes, it referred as Track and Hold (T/H) .The important parameters of S/H circuit are: hold step, signal isolation in hold mode, input signal tracking speed in sample mode, droop rate in hold mode, aperture jitter. The basic schematic of sample and hold circuit is as shown in fig.6.8.

          Fig.3.2: Sample and Hold Circuit CMOS Layout of Sample and Hold Circuit

          Fig.3.4: Basic schematic of Comparator

          The basic Gates of comparator are

          1. EX-OR with 6 transistor

            Fig.3.5: Basic schematic of EX-OR with 6 transistors

          2. AND Gate

    Fig.3.6: Basic AND Gate

    Fig.3.7: Basic schematic of AND Gate CMOS layout of Comparator

    Fig.3.8: CMOS layout of Comparator


    The proposed work is to design SAR ADC by using CMOS technology. First of all the basic schematic is drawn by using DSCH 3.5 software. And it is verified by using this software. Then CMOS layout is drawn based on basic schematic design by using Microwind 3.1 software. And then verification is done for various parameters.

    Fig.4.1: Proposed Model Flow


    Fig.5.1: Simulation result for Sample and Hold circuit

    Fig.5.2: Simulation result for Comparator


In this paper, we proposed the basic schematic and simulation result of Sample and Hold circuit and Comparator which are useful for the further processing of SAR ADC.


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