# Design of current Mirror and Temperature Effect with Compensation technique

DOI : 10.17577/IJERTV1IS3062

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#### Design of current Mirror and Temperature Effect with Compensation technique

Design of current Mirror and Temperature Effect with Compensation technique

Praween kumar sinha.M..A.I.T, Delhi.

#### DR K.S .YADAV PROF &HOD ECE N IEC DELHI

INTRODUCTION

A current mirror replicates the input current of a current sink or current source as an output current. The output current may be identical to the input current or can be a scaled version of it. A current mirror is a circuit designed to copy a current through one active device by controlling the current in another active device of a c ircuit, keeping the output current constant regardless of loading.

The current being 'copied' can be, and sometimes is, a varying signal current. Conceptually, an ideal current mirror is simp ly an ideal inverting current a mplifier that reverses the current direction as well or it is a current-controlled current source (CCCS). The current mirror is used to provide bias currents and active loads to circuits… Mirror characteristics There are three main specifications that characterize a current mirror.The first is the transfer ratio (in the case of a current amp lifier) or the output current magnitude (in the case of a constant current source CCS).The second is its AC output

resistance, which determines how much the output current varies with the voltage applied to the mirror.The third specification is the minimu m voltage drop across the output part of the mirro r necessary to make it work properly.Th is minimu m voltage is dictated by the need to keep the output transistor of the mirror in active mode. The range of voltages where the mirror works is called the compliance range and the voltage marking the boundary between good and bad behavior is called the compliance voltage.

KEY WORD:MOSFET ,CURRENT MIRROR, COMPANSAT ION TECHNIC.

Temperature dependency

The temperature dependency analysis gives us relation between Iout and temperature.

For a M OSFET the te mperature dependent parameters are :

1. Mobility (Âµ(T))

2. Threshold Voltage(Vi(T))

Mobility and threshold voltage depends on temperature according to following re lations:

Âµ (T) = Âµ(T0)-3/2

Vt(T) = Vt (To) – (T- To)

Where

Âµ (T0) = 400 c m2 V-1S-1 and = 2.3 mV/0C

Temperature compensation technique

The variations of a current shown to the absolute temperature can be classified into two broad categories:

1. Proportional to absolute temperature (PTAT)

2. Inversely proportional to absolute temperature (ITAT)

The basic idea to have a first order temperature compensation is to add a PTAT current with an ITAT current. This way, the current which is obtained would show a much slower variation compared to the original PTAT or ITAT currents.The individual currents are generated by using a self-biased feedback loop. The circuit used in both the loops is the same but the two loops have been designed to give opposite temperature coeffic ients of current. After obtaining these PTAT and ITAT currents we add

both these currents to obtain a fairly constant current with respect to temperature variations.

Fig.1 shows the idea of this first order temperature compensation.

Specifications

• Id =20 ÂµA Vdd,Vgs = 1.5V

• R1=10KR2=10 K,

• 15 K,20 K

• R01=10 K

• R02=0K

Model parameter

• Vgs = 1.5V

• KÂ´N = 24.0 ÂµA/ V2

• KÂ´P =8.0 ÂµA/ V2

• VTN =-VTP = 0.75 V

• N =0.01/ V

• P =0.02/ V

simple C.M aspect ratio

By applying the model para mete rs values, we get : S 2.96

=>S = 3

T-spice coding for simp le C.M :

vdd 1 2 dc 1.5v

vgnd 2 0 dc 0v

M1 1 1 2 2 n mos1 w=3u l=1u

M2 3 1 2 2 n mos1 w=3u l=1u

R 1 3 10k

.MODEL NMOS1 NM OS VTO=0.75 KP=24U LAM BDA=0.01

.DC VDD 0V 1.5V 0.01V

.temp 0 27 75

.PRINT DC ID(M 2), id(m1)

.OP

.END VDD VDD

M 1 M2

Fig2: simple Current Mirror

Fig3: Without Temperature compensation simple

Aspect ratio calculat ions

By applying the model para mete rs values, we get: S =2.96

S=3=>s1=s2=s3=s4

For M5:

When R1= R2 = 10K Vds(M2) =1.26V

Vgs(M5)

By putting the values we get, S5 = 3.2

Similarly Fo r M6:

Case 1: when R=10K S6 = 3.2

Case 2: when R=15K Vgs(M6) =1.1455V

=> S6 = 5.32

Case 3: when R=20K Vgs(M6) =1.089V

=>S6 = 7.25

For M7:

Vds(M5) = Vgs – Vt = 0.51 Vg (M5) = 0.51

Vsg(M5) = Vs Vg = 1.5 0.51

Vsg=.99v

putting these values in saturation drain current equation. we get,S7=34.72

3) R2= 20K

VDD 1 2 DC 1.5V

VGND 2 0 DC 0V

M 1 1 1 2 2 NM OS1 W=3U L=1U

M 2 3 1 2 2 NM OS1 W=3U L=1U

M 3 1 1 2 2 NM OS1 W=3U L=1U

M 4 5 1 2 2 NM OS1 W=3U L=1U

M 5 4 3 2 2 NM OS1 W=3.2U L=1U

M 6 4 5 2 2 NM OS1 W=7.25U L=1U

M 7 4 4 1 1 PM OS1 W=34.7U L=1U

R1 1 3 10K

R2 1 5 20K

.MODEL NM OS1 NMOS VTO=0.75 KN=24U LAM BDA=0.01

.MODEL PM OS1 PMOS VTO=-0.75 KN=8U LAM BDA=0.02

.DC VDD 0 1.5V 0.01V

.TEM P 0 27 75

.PRINT DC ID(M 7)

iD(M7) (uA)

.END

CM2

iD ( M 7 )

0

– 5

– 1 0

– 1 5

– 2 0

– 2 5

0 .0 0 .5 1 .0 1 .5

VDD (V)

Fig 5. Without T emperature compensation

Fig 6. Layout of temp. compensated Simple Current Mirror

Fig 7. Layout of temp. compensated Simple Current Mirror

VGND 2 0 DC 0V

M1 1 3 2 2 NMOS1 W=3.5U L=1U

M2 4 1 2 2 NMOS1 W=3.5U L=1U

R01 1 3 10K

R1 1 4 10K

.MODEL NMOS1 NM OS VTO=0.75 KN=24U LAM BDA =0.01

.DC VDD 0V 1.5V 0.01V

.TEMP 0 27 75

.PRINT DC ID(M2)

.OP

iD(M2) (uA)

.END

1

iD ( M 2 )

2 5

2 0

1 5

1 0

5

0

0 .0 0 .5 1 .0 1 .5

VDD (V)

Fig8.Without Temperature compensation

Fig 9. Layout of Modified Current Mirror

Fig 10 With temperature compensation

Aspect ratio calculat ion

1). As pect Rati o

K W V V

' 2

I n gs t

d 2L

Vsg(M5) = Vs Vg = 1.5 0.51

Vsg=.99v

putting these values in saturation drain current S7=34.72

3) R2=20K

VDD 1 2 DC 1.5V

VGND 2 0 DC 0V

M1 1 3 2 2 NMOS1 W =3U L=1U

M2 4 1 2 2 NMOS1 W =3U L=1U

M3 1 7 2 2 NMOS1 W =3U L=1U

M4 6 1 2 2 NMOS1 W =3U L=1U

M5 5 4 2 2 NMOS1 W =3.2U L=1U

M6 5 6 2 2 NMOS1 W =7.25U L=1U

M7 5 5 1 1 PM OS1 W=34.7U L=1U

R01 1 3 10K

R02 1 7 10K

R1 1 4 10K

R2 1 6 20K

.MODEL NMOS1 NM OS VTO=0.75 KN=24U LAM BDA =0.01

.MODEL PMOS1 PMOS VTO=-0.75 KN=8U LAMBDA=0.02

.DC VDD 0 1.5V 0.01V

.TEMP 0 27 75

.PRINT DC ID(M7)

.END

1

iD ( M 7 )

By applying the model para mete rs values, we get : S=2.96

=>S=3

=>S1=S2=S3=S4

0

– 5

iD(M7) (uA)

– 1 0

For M5:

When

R1= R2 = 10K Vds(M2) =1.26V

Vgs(M5) =1.26V

– 1 5

– 2 0

– 2 5

0 .0 0 .5 1 .0 1 .5

VDD (V)

By putting the values we get, S5 = 3.2

Similarly For M6:

Case 1: when R=10K

S6 = 3.2

Case 2: when R=15K

Vgs(M6) =1.1455V S6=5.32

Case 2: when R=20K

Vgs(M6) =1.089V

Fig11. With Temperature compensation technique R=20k

S6=7.25

For M7:

Vds(M5) = Vgs Vt = 0.51 Vg (M5) = 0.51

Fig12 Layout of Temperature Compensated Modified CM

1. Simple current mirror

1. Without compensation technique

1. Without compensation technique

 INPUT CURRENT Iout1T =27c Iout2T =75c 20 uA 3.35 Ua 7.68 uA
2. With co mpensation technique

 Input Current Iout1 T =2 7 Iout2 T =75 R1 R2 (w/l)Of M6 1.20uA 1.73 4.57 10 10 3.2 2. 20uA 0.5 9 2.64 10 15 5.32 3. 20uA 0.7 8 .78 10 20 7.25
3. Modified current Mirror

 INPUT CURRENT Iout1T =27c Iout2T =75c 20 uA 4.35 Ua 7.44 uA
4. Modified current Mirror

 Input Current Iout1 T =27 Iout2 T =75 R1 R2 (w/l)Of M6 1.20uA 1.53 4.45 10 10 3.2 2. 20uA 2.63 0.64 10 15 5.32 3. 20uA 0.49 9 0.499 10 20 7.25

CONCLUS ION

The T-spice simulat ion and layout of compensated simp le current mirror and modified current mirror were successfully designed and tested under the specification of 20uA current.

The result obtained is fairly desirable as fo llo ws:

1.Fo r simple current mirror without temperature compensation:

With the change in temperature fro m 0-25C the current has a variation of 3.56 uA.And with further change in temperature fro m 0-75C the current has a variat ion of 7.44 uA.

W ith the use of temperature compensation technique, the current variation for simple current mirror in 0 – 25C and 0-75C scale has been reduced to .78 uA which proves the fact that temperature compensation technique has a constant output current irrespective of change in the temperature.

Similarly in Te mperature co mpensated modified current mirro r the current variation has been reduced to .499 uA with the temperature variations of 0-25C and 0-75C.

1] R. Kenyon, "A Quick Guide to Voltage eferences,"

EDN, no. 8, pp.161-167, April 13, 2000.

1. AS. Sedra and K.C. Smith, Microelectronic Circuits.

New York: Holt,Rinehart and Winston, 1987.

2. A. Hastings, The Art of Analog Layout. New Jersey:

Prentice-Hall, Inc.,2001.BIBLIOGRAPHY 21

3. M. Guna wan et. al., "A Curvature-Corrected Low-Voltage BandgapReference," IEEE Journal of Solid-State Circuits, vol. 28, no. 6, pp.667-670, June 1993.

4. A.L. Coban and P.E. A llen, "A 1.75 V Rail-to-Ra il CMOS Op Amp,"Proceedings IEEE International Symposium on Circuits and Systems, vol. 5,pp. 497-500, 1994.

5. M. He lfenstein et. al., "90 d B, 90 M Hz, 30 mW OTA with the Gain-Enhance ment Imple mented by One- and Two-Stage Amplifie rs," ProceedingsIEEE International Symposium on Circuits and Systems, vol. 3,pp. 1732-1735, 1995.

6. P.R. Gray and R.G. Meyer, Analysis and Design of Analog IntegratedCircuits. New York: W iley, 1993.

7. Y.P. Tsividis, "Accurate Analysis of Temperature Effects in Ic – VbeCharacteristics with Application to Bandgap Reference Sources," IEEE

Journal of Solid-State Circuits, vol. SC-15, no. 6, pp. 1076-1084, Dece mber1980.[9] G.M. Me ijer et. al., "A New Curvature- Corrected Bandgap Reference,"

IEEE Journal of Solid-State Circuits, vol. SC-17, no. 6, pp. 1139-1143,Dece mber 1982.

[[9] F. Fiori & P.S. Crovetti, Co mpact mperatureco mpensated CMOS current reference, Electronics Letters, Vol. 39 – No.1

1. C. Yoo & J. Park, CM OS Cu rrent refe rence withsupply and

temperature co mpensation, Electronics Letter Volu me 43 No.25.

2. Zhou Hao, Zhang Bo, Li Zhao-ji, Luo Ping, ANe w CMOS

Current reference with high OrderTe mperature Co mpensation, 0-7803-9584-0/06/\$20.00-2006IEEE

3. B. Ra zavi, Design of Analog CMOS Integrated

Circuits, Tata Mc Graw Hill Edit ion 2002.