Design and Implementation of 8T SRAM at 18nm FINFET Technology in Cadence Virtuoso

DOI : 10.17577/IJERTV11IS050324

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Design and Implementation of 8T SRAM at 18nm FINFET Technology in Cadence Virtuoso

Vemula Panduranga,

Associate professor,Dept. of ECE, CMR College of Engineering & Technology,

Medchal, Hyderabad, Telangana, India.

Chaganti Prathyusha UG Student, Dept. of ECE,

CMR College of Engineering & Technology, Medchal, Hyderabad, Telangana, India.

AbstractSRAM is an important component of any memory system; SRAMs are faster and more dependable, and they're frequently utilised as a memory cache in digital processors for high-speed operations. The primary goal of device scaling or the application of diverse technologies is to reduce power consumption. The main issue with technology scalability is power consumption and device stability. To solve the problem of power dissipation and stability in nanoscale technology, various topologies of SRAM have been proposed. FinFET-based devices have shown to be a better option for SRAMs with reduced power dissipation. In low-power applications, process differences must be considered in low-dimension devices. At the moment, the main goal is to reduce power consumption. The lower the power consumption of SRAM cells, the better. This research offers a new 8T (8 transistor) SRAM configuration that improves reading and writing latency while reducing leakage power. With 18 nm FinFET technology, the Cadence Virtuoso tool is utilised to analyse process corner analysis.

Keywords 8T SRAM,, FinFET, read, write, leakage power, Nanometer, Nanoscale, CMOS, IC memory.


    In memory-rich network-on-chip (SoC) designs, embedded SRAMs are a vital component. They're employed as buffer memories or caches, and they take up a lot of space in today's VLSIs. Subthreshold SRAM designs to extend system working life-time from limited energy resources have become an ever-important challenge, particularly in energy- constrained low-speed biomedical devices and other developing applications such as wireless sensor networks and various wearable devices.

    Chip Storehouse makes up the bulk of chips, and its use in mobile bias and high- end processors is projected to increase in the future. Roe Power Cache is needed in movable operations to achieve high responsibility and long battery life. Bias come more responsive to sound sources as CMOS technology improves at thesub-micrometer position. Small- area, high- viscosity nanoscale bias make up moment's SystemsonaChips (SoCs) and other intertwined circuits. This generates substantial hindrance with other rudiments of the system from power lines and other signal sources in the sound generating chain. The fact that SRAM is made up of a number of little audio sensitive bias is one illustration of a system where acoustics is a bigissue.The trustability of

    SRAM cells is one of the major challenges. The perceptivity of the memory to reuse forbearance and operating circumstances is determined by cell stability. When there's a sound signal, it should work typically. As a result, SRAM module power consumption should be reduced to a minimum, and the specialized literature should be completely examined. Developing SRAM cells with veritably minimum functionality is the most effective approach to attain this thing. The thing of this paper is to offer a new 8T SRAM cell that reduces power consumption while perfecting read and write delay.

    Semiconductor memory is divided into two categories. Emile RAM (SRAM) is made up of a flip-flop, which is a bistable circuit with 4 to 6 transistors. If the trigger is held for a brief time, the value will be retained until the opposite value is stored. Although SRAM allows for faster data access, it is physically larger. It is mostly used in the central processing unit (CPU) of a computer and a tiny amount of memory known as registers in fast "store" memory. Instead than using a flip-flop, dynamic RAM (DRAM) uses transistors as charging switches or discharging capacitors to store each component in an electrical capacitor. The final DRAM cell is smaller than SRAM because there are fewer electronic components. The stored value must be charged around 50 times per second because access to that value is slow and the capacitor's charge flows slowly. However, because a chip of the same size may contain several times more DRAM than SRAM, DRAM is frequently utilised as the main memory.

    FINFET transistors are used in various Integrated circuits because the three dimensional structure of FINFET offers much flexitybility for the same size they provide much density. Recently the use of FINFETs in Integrated circuits is increased drastically. FinFET transistor technology has some important advantages in IC design over the more common planar technology.FinFET technology is expected to give greater levels of scalability,allowing current advances with more integration.It is considered long way forward to be included in Integrated Technology because of its numerous advantages in processing, data storing ,speed etc. FinFET technology was created as a result of the continuous rise in integration levels.

    As we know that every two years, the number of transistors on a particular area of silicon doubles.Even though they were advanced with the time some chip of early integrated circuit period had a low transistor count.Many orders of magnitude more are available today. Many parameters been adjusted to accomplish the huge increases in integration levels. Fundamentally, feature sizes have shrunk to allow for the fabrication of more devices in a given space.Other numbers, like as dissipation of power and voltage, have decreased as frequency performance has improved. Individual device scalability has its limits, and as process technologies shrank to20 nm.Then it became difficult to a scale different device parameters correctly. The supply voltage power which helps in determining dynamic power also got affected.Optimisation of one variable affected the other variables.As a results change in transistor structure from planar was considered.Another concern is that as power the source terminal and drain terminal advanced into channel making leakage current to flow easily but making it hard to turn off transistor.

    The name FINFET come from the fin shaped structure of transistor when seen. FinFETs are three-dimensional structures that rise above the substrate and look like a fin.The FINs serve like source terminal and drain terminal,allowing larger density as that of a standard planar tranistor.As gate is wrapped around the FIN structure which provides more control over the channel because of it larger length.And a very low current leakage is absorbed when it is turned off.Which allows threshold voltage to lower and results improved performance and decreased dissipation of power.

    Fig 1. Structure of FINFET

    It wraps around the fin to get from one side to the other, allowing it to interact with three sides of the fin or channel. This type of gate layout allows for better electrical control of channel conduction, as well as lowering level of leakage current and overcoming several other short-channel effects. It's also sometimes used to refer to any FIN type multiple gate transistor design, irrespective of gate count.IC makers are leveraging FinFET technology in a variety of ways to boost the density of their chips without sacrificing performance of device.



    Feature dimensions

    It is possible to break beyond the 20nm barrier, which was previously regarded to be the limit.


    The consume less power

    voltage of operation

    Because of their lower threshold voltage, they have lower operation voltage.

    Speed of operation

    FinFET variants are frequently 30 percent quicker.

    Static leakage current

    Decreased up to 90% in most cases

    Table .1.Benifits of FINFET Technology


    Fig 2. proposed 8T SRAM cell

    As shown in Figure 2, the proposed SRAM cell consists of eight transistors which include five FinFET NMOS transistors NM0,NM1,NM2,NM3,NM4 and 3 FinFET PMOS transistors PM3,PM4,PM5 . The four transistors NM3, NM4, PM3, and PM4 form a latch setup to store data, which remains in a loop until it is available. Internal nodes Q and QBAR are accessed via two access transistors NM1 and NM2. NM1 and NM2 connect the internal nodes of cells Q and QBAR. PM5 and NM0 work together to forms a inverter that controls voltage at node C, while NM1 and NM2 connect internal cell nodes to bit lines, where nodes Q and QBAR play critical roles in read and write operations. Its always precharged to Vdd when we use bit_line and bit_linebar while reading operation . The CS line is connected to the PM3 and PM4 source terminal and the WL line is connected to the gate terminals of PM5 and NM0. The origins of the PM3 and PM4 are different from conventional designs. The PM3 and PM4 source terminals are connected to a flexible VDD line, which is boosted to a high voltage during the sensing function to provide greater headroom unlike standard designs.

    Read Operation

    In order to read operation , the word_line in SRAM must be raised to high. Memory should hold a certain value in order to carry out the read operation . Consider the case where memory holds Q = 1 and QBAR = 0. To finish the read operation, raise the word line to the highest setting. The access transistors NM1 and NM2 are now active. The output lines BIT and BIT BAR are precharged when the node voltage hits Vdd.Since both Q and BIT line are high, there is no voltage difference between them and there will be no dropdown in the voltage . since QBAR is low and BIT_BAR is high there is a voltage difference between them , which causes drop in the voltage BIT_BAR line. As a result, the circuit will discharge and the current will flow. The sensing amplifier is linked to BIT and BIT_BAR and it functions as a comparator and produces output by amplifying the voltage difference between BIT and BIT_BAR thus, the output is 1 when the BIT_BAR is low i.e Q=1 is present in the latch.

    BIT_BAR thus, When the BIT is low, i.e. Q=0 is present in the latch, the output is 0.

    Write Operation

    Fig.4.waveforms -Read operation

    Fig. 3. 8T SRAM using 18nm FINFET Technology-Read circuit

    In other case consider memory holds Q = 0 and QBAR = 1 as an example.To finish the read operation, raise the word line to the highest setting. The access transistors NM1 and NM2 are now active. The output lines BIT and BIT BAR are precharged when the node voltage hits Vdd. Since both QBAR and BIT_BAR line are high, there is no voltage difference between them and there will be no dropdown in the voltage . since Q is low and BIT is high there is a voltage difference between them , which causes drop in the voltage BIT line. As a result, the circuit will discharge and the current will flow. The sensing amplifier is linked to BIT and BIT_BAR and it functions as a comparator and produces output by amplifying the voltage difference between BIT and

    When a write cycle begins,the logic to be written into memory is applied on the bit_lines.If you wish to put zero in the memory set BIT to 0 and BIT_BAR LINE to 1.Or if you wish to put one in the memory then set BIT to 1 and BIT_BAR to 0.After passing in the value to be stored,The bit line input drivers are meant to be far more powerful than the cell's comparatively weak transistors, allowing themto quickly overcome the cross-coupled inverters' prior state.In the suggested architecture, writing is far easier than reading.

    Fig.5. 8T SRAM using 18nm FINFET Technology-write circuit

    The writing procedure starts by rising to Vdd while the Wordline(WL) is being brought down.One BLS is being held at VDD while the other is being dragged to the ground.NM3 and NM4 are charged to VDD when the node is turned on.Both NM3 and NM4 are charged when node C is charged to VDD. When NM-3 and NM-4 are turned on, input data is copied into memory in the same way that it would be in a conventional 6T SRAM.

    Fig.6. Waveforms -Write operation






    FinFET 18nm (above architecture)

    Leakage Power

    26.89 µW

    66.89 µW

    1.022 µW

    Read Delay

    76.78 ps

    28.98 ps

    6.41 ps

    Write Delay

    6.71 ps


    73.38 ps

    Table 2: Performance comparison between CMOS-180nm 8T SRAM cell, CMOS-45nm 8T SRAM cell, and FinFET18nm 8T SRAM cell

    The leakage power of 8T SRAM at FINFET 18nm is clearly lower than that of existing 8T SRAMs using CMOS-180 nm and CMOS-45 nm technologies, as shown in the table above. Also, when compared to 8T SRAMs at CMOS-180 nm and CMOS-45 nm technologies, read and write delays are

    significantly reduced. As a result, the current architecture is the best in terms of read and write delay, as well as leakage power.


    The design of an 8T SRAM cell on 18nm FinFET is described in this paper. After demonstrating harmonious affair recovery on write and read operations, the design was completed. This research also contains a thorough evaluation of two conventional 6T and 8T SRAM cells based on multiple well-studied 18nm FinFET devices.

    Delays have also been investigated and compared to previous models, and 8T SRAM cells using 18nm FinFET technology are stable for read operations.The 8T cell has been proposed to reduce BIT line leakage, making it suitable for use as a cache memory in internal CPUs and low-power applications.


[1] Shreelakshmi, Sendamarai P Enhancement of Design Quality for an 8- bit ALU ABHIYANTRIKI an international journal of engineering and technology (AIJET) Vol. 3, No. 5 (May, 2016).

[2] Moradi, F., Madsen, J.K.: Improved read and write margins using a novel 8T-SRAM cell. In: 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC), pp. 1, 5, 68 October 2014.

[3] Kevin Z. Embedded Memories for Nano-Scale VLSIs. Springer Publishing Company,Incorporated. 2009; 400.

[4] Takeda K. et al. A read-static-noise-margin-free SRAM cell for low- VDD and high-speed applications. Solid-State Circuits, IEEE Journal of 2006; 41(1): 113-121.

[5] Do Anh-Tuan et al., A 8T Diffrential SRAM With Improved Noise Margin for Bit-Interleaving in 65nm CMOS, IEEE transactions on circuits and systems,vol.58, no.6,pp.1252-1263, June 2011.

[6] T.-H. Kim, J. Liu, and C. H. Kim, "A voltage scalable 0.26 V, 64 kb 8T SRAM with voltage lowering techniques and deep sleep mode," IEEE

J. of Solid-State Circuits, v. 44, no. 6, pp. 1785-1795, Jun. 2009.

[7] N. Verma and A. P. Chandrakasan, "A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy," IEEE J. of Solid-State Circuits, vol. 43, no. 1, pp. 141-149, Jan. 2008.

[8] L. Sun, J. Mathew, R. A. Shafik, D. K. Pradhan, and Z. Li, A low power and robust carbon nanotube 6T SRAM design with metallic tolerance, in Proceedings of the 17th Design, Automation and Test in Europe (DATE '14), March 2014.

[9] Benton H. Calhaun, Anantha P. Chandrakasan Static Noise Margin Variation for Sub-threshold SRAM in 65 nm CMOS, IEEE Journal of Solid-State Circuits,, pp.1673-1679. vol.41,July 006.

[10] Benton H. Calhoun, Yu Cao, Xin Li, Performance Evaluation of Emerging Devices Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS, in Proceedings of the IEEE, 2008, vol. 96, no.2, pp.342-365.

[11] R. W. Keyes, The effect of randomness in the distribution of impurity atoms onFET thresholds, App. Phys. A: Materials Science & processing, vol. 8, no. 3, pp.251259, Jun. 1975.

[12] Bhuvaneshwari, Y. V., et al. "SEU study of 4T, 6T, 7T, 8T, 10T MOSFET based SRAM using TCAD simulation." Information Communication and Embedded Systems (ICICES), 2014 International Conference on. IEEE,2014.

[13] S. M. Salahuddin, H. Jiao and V. Kursun, "A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability", Quality Electronic Design (ISQED) 14th International Symposium on, pp. 353-358, 2013.

[14] R.V. Joshi, R.Q. Williams, E. Nowak, K. Kim, J.Beintner, T. Ludwig,

I. Aller, and C. Chuang,"FinFET SRAM for high-performance low- power applications", Proceeding of the 34th European Solid-State Device Research conference, pp. 69 – 72, 2004.

[15] Alluri S (2019) High performance SR latch in VLSI circuits using FINFET 18nm technology. J Continua Math Sci ISSN 14(6):329346

[16] Nanda S, Dhar RS Implementation and characterization of 14 nm trigate HOI n-FinFET using strained silicon channel with reduced area on chip. In: 6th international conference for convergence in technology (I2CT), pp. 14. IEEE, India (2021).

[17] D. Bhattacharya and N. K. Jha, Ultra-High Density Monolithic 3-D FinFET SRAM with Enhanced Read Stability, IEEE Transactions on Circuits and Systems, Vol.63, No. 8, pp. 1176-1184, August 2016.

[18] T. Cakici, K. Kim and K. Roy, "FinFET Based SRAM Design for Low Standby Power Applications," 8th International Symposium on Quality ElectronicDesign(ISQED'07),2007,pp.127-132.

[19] Medeiros, Guilherme Cardoso,Development of a test methodology for FinFET-Based SRAMs, PhD thesis, Pontifical Catholic University of Rio Grande do Sul – PUCRS (2017).

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