Concurrent Error Detectable Multiplier with Observing Point Insertion

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Concurrent Error Detectable Multiplier with Observing Point Insertion

J. Nayanadhara1, Dr. M. Revathy2,

PG Scholar,Department of ECE, PSNA CET, Dindigul, India1 Associate Professor, Department of ECE, PSNA CET, Dindigul, India2

Abstract:- Concurrent Error Detection (CED) methods (in light of equipment duplication, equality codes, and so on.) are broadly used to upgrade framework constancy. All CED methods present some type of excess. Excess frameworks we subject to normal mode disappointments (CMFs). While a large portion of the investigations of CED systems center around region overhead, few break down the CMF defenselessness of these methods. In this paper, we present reenactment results to quantitatively think about different CED plans dependent on their region overhead and the assurance (information trustworthiness) they give against numerous disappointments and CMFs. Our outcomes demonstrate that, for the recreated combinational rationale circuits, albeit various duplex frameworks (with two distinct executions of a similar rationale work) in some cases have barely higher zone overhead, they give noteworthy insurance against numerous disappointments and CMFs contrasted with other CED systems like equality forecast

Index terms Concurrent Error Detection, Multiplier and Built-In Error Detection (BIED).

  1. INTRODUCTION

    configurations for the betterment of reliability at the cost of area[10]. A effectual VHBCSE algorithm for FIR filter is employed for 4 bit in addition to 8 bit common sub- expression elimination [11].Self-checking full adder and the self-repairing full adder circuit. A proposed self- checking circuit designed such that it can find transient as well as permanent fault depend on internal process and it is able to detect multiple faults at the same time[12].If the design of four bit fault tolerant ripple carry adder and also discuss how design costs and number of faults to be tolerated are affected with the size of sub-module chosen to make the system self-reconfigurable[13].A new fault model that suits the characteristics of these devices, and report the results of a SPICE-based analysis of the effects of faults on the behavior of some basic gates implemented with them[14].A self-checking Carry Select Adder (CSA) with fault localization ability.It provide minimum area overhead for self-recovery process because instead of replacing the whole system we can now replace the particular faulty modules[15].

    Fault-tolerant mechanism for the ALU, called LIZARD [1].A novel inner product (IP) design for stochastic computing[2].A high-performance low-power carry speculative adder (CSPA). This adder separates the carry generator and sum generator. Only one sum generator is used in a block adder to reduce the critical path delay and area overhead[3].A low energy consumption block-based carry speculative approximate adder. [4] A technique for designing carry-free adders with on-line error checking capability. The adders use signed binary digits (SBDs) internally [5]. A new implication reduction algorithm that guarantees no loss on Pdetection.The detectability of errors for each candidate implication is carefully evaluated [6]. A testable EDL (TEDL) architecture for manufacturing and field testing. Fault coverage and area overhead are illustrated on a resilient implementation of Plasma, a 3- stage OpenCore MIPS CPU, which contains the proposed testable EDL circuitry [7]. It will be describes a new approach of full adder (FA) to accomplish fault-tolerant adder designs, which are more efficient than the conventional approaches, in distinct characteristic against many errors[8].A hybrid approximation methodology based on error tolerant multipliers (ETMs).The proposed design splits the approximation process into two parts:(1) approximating the most significant bits (MSBs) using approximate logarithms and (2) approximating the least significant bits (LSBs) using truncation[9].Emphasizes on fault-tolerant carry save adder using hardware redundancy

  2. LITERATURE SURVEY

    SeokinHong et al [1] propose a novel cost-efficient fault- tolerant mechanism for the ALU, called LIZARD. LIZARD employs two half-word ALUs, instead of a single full-word ALU, to perform computations with concurrent fault detection. When a fault is detected, the two ALUs are partitioned into four quarter-word ALUs.

    Werner Haselmayr et al [2] present a novel inner product (IP) design for stochastic computing (SC). SC is an emerging computing technique, that encodes a number in the probability of observing a one in a random bit stream. This leads to reduced hardware costs and high error tolerance.

    Ing-Chao Lin et al [3] proposes a high-performance low- power carry speculative adder (CSPA). This adder separates the carry generator and sum generator. Only one sum generator is used in a block adder to reduce the critical path delay and area overhead

    FarhadEbrahimi-Azandaryani et al [4] proposed a low energy consumption block-based carry speculative approximate adder . Its structure is based on partitioning the adder into some non-overlapped summation blocks whose structures may be selected from both the carry propagate and parallel-prefix adders

    P.K. Lala et al [5] presented a technique for designing carry-free adders with on-line error checking capability.The adders use signed binary digits (SBDs) internally. An adder consists of sign-magnitude binary to SBD converters, an intermediate adder block that generates partial sum and carry digits, a second adder block that produces a sum digit computed from a partial sum and a partial carry digit, and an error checker that indicates whether the code word corresponding to a final sum digit is error-free or not

    A. Jaekel et al [6] develop a new implication reduction algorithm that guarantees no loss on Pdetection.The detectability of errors for each candidate implication is carefully evaluated. The evaluation results are then utilized to select the most efficient candidates for detecting all the detectable errors.

    Felipe A. Kuentzer et al [7] proposes a testable EDL (TEDL) architecture for manufacturing and field testing. Fault coverage and area overhead are illustrated on a resilient implementation of Plasma, a 3-stage OpenCore MIPS CPU, which contains the proposed testable EDL circuitry.

    PrachiPalsodkar et al [8] describes a new approach of full adder (FA) to accomplish fault-tolerant adder designs, which are more efficient than the conventional approaches, in distinct characteristic against many errors. This design covers self- checking and self-repairing FA to achieve multiple error detection and correction capability of all multiple permanent & transient errors.

    Aly Sultan et al [9] introduced a hybrid approximation methodology based on error tolerant multipliers (ETMs).The proposed design splits the approximation process into two parts: (1) approximating the most significant bits (MSBs) using approximate logarithms and

    (2) approximating the least significant bits (LSBs) using truncation.

    T.Nirmalraj et al [10] emphasizes on fault-tolerant carry save adder using hardware redundancy configurations for the betterment of reliability at the cost of area.

    [11].N.Mahalakshmi et al proposed a effectual VHBCSE algorithm for FIR filter is employed for 4 bit in addition to 8 bit common sub-expression elimination.

    Sonalgupta et al [11] proposed self-checking full adder and the self-repairing full adder circuit. A proposed self- checking circuit designed such that it can find transient as well as permanent fault depend on internal process and it is able to detect multiple faults at the sme time.

    Atin Mukherjee et al [12] design a four bit fault tolerant ripple carry adder and also discuss how design costs and number of faults to be tolerated are affected with the size of sub-module chosen to make the system self-reconfigurable.

    1. Ghasemzadeh et al [13] propose a new fault model that suits the characteristics of these devices, and report the results of a SPICE-based analysis of the effects of faults on the behavior of some basic gates implemented with them.

      Muhammad Ali Akbar et al [14] proposed a self-checking Carry Select Adder (CSA) with fault localization ability. It provide minimum area overhead for self-recovery process because instead of replacing the whole system we can now replace the particular faulty modules.

      AlirezaNamazi et al [15] proposed error correction technique is compatible with all existing error detection techniques which are proposed for the CSA adder.

  3. RESULT AND DISCUSSION

    The experimental results show that the proposed CSPA achieves a 26.59% delay reduction, a 14.06% area reduction, and a 19.03% power consumption reduction compared to the corresponding values for an existing speculative carry-select adder. Area overhead of the proposed adder is 25% less, Power delay product of 4 bit fault tolerant multiplier is 92% less compared to Triple Modular Redundancy (TMR) method. We finally exploit this property to build a robust and scalable adder whose area, performance and leakage power characteristics are improved by 15%, 18% and 12%, respectively, when compared to an equivalent Fin FET solution at 22-nm technology node.

  4. CONCLUSION

Array multipliers consist of full adders (FAs). When the sums and carrys are propagated down through the array, each row of FAs is used only once. Most FAs are doing no useful work at any given time. In this work propose a new design concurrent error-detectable array multiplier using observation point insertion. A heuristic design-for- checkability method based on observation point insertion in the Circuit Under Check (CUC) is proposed to increase the error detection ability of Concurrent Checkers (CC).As a result, both normal and repeated operations are performed in one single set of hardware simultaneously. The analysis show that the our implementation has the following significant benefits: (i) It has a moderate hardware overhead, but little performance degradation and (ii) The time and hardware overheads are constant for detecting both single and multiple faults

REFERENCES:

    1. Seokin Hong and SoontaeKim, A Low-Cost Mechanism Exploiting Narrow-Width Values for Tolerating Hard Faults in ALU,IEEE Transactions on Computers( Volume: 64 , Issue: 9, Sept. 1 2015 )

    2. Werner Haselmayr, Daniel Wiesinger and Michael Lunglmayr

      ,High-Accuracy and Fault Tolerant Stochastic Inner Product Design,IEEE Transactions on Circuits and Systems II: Express Briefs( Early Access ).

    3. Ing-Chao and Lin Yi-Ming Yang Cheng-zChian Lin,High- Performance Low-Power Carry Speculative Addition With Variable Latency, IEEE Transactions on Very Large Scale Integration (VLSI) Systems( Volume: 23 , Issue: 9 , Sept. 2015 ).

    4. Block-based Carry Speculative Approximate Adder for Energy- Efficient Applications,IEEE Transactions on Circuits and Systems II: Express Briefs ( Early Access ).

    5. P.K.Lala A. Walker On-line error detectable carry-free adder design,Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

    6. A. Jaekel On-line error detection in multiplexor based FPGAs,IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( Volume: 37 , Issue: 5 , May 2018 ).

    7. Felipe A. Kuentzer Leonardo R. Juracy Matheus T. Moreira Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template, 2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI).

    8. PrachiPalsodkar, PrasannaPalsodkar and RupaliGiri Multiple Error Self Checking-Repairing Fault Tolerant Adder- Multiplier,2018 IEEE Region 10 Humanitarian Technology Conference (R10-HTC).

    9. AlySultan, Ali H.Hassan and HassanMostafa A Compact Low- Power Mitchell-Based Error Tolerant Multiplier 2018 New Generation of CAS (NGCAS).

    10. T.Nirmalraj S.Ashwin V.Elamaran Rakesh Kumar Karn Fault Tolerant Carry Save Adders – A NMR Configuration Approach,2018 International Conference on Control, Power, Communication and Computing Technologies (ICCPCCT).

    11. N.Mahalakshmi, P.Banupriya,An efficient constant multiplier architecture with error correction codes 2016 International Conference on Advanced Communication Control and Computing Technologies (ICACCCT).

    12. Sonalgupta,Ashishjasuja and RahulShandilya Real-time fault tolerant full adder using fault localization 2018 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS).

    13. Atin Mukherjee ,AnindyaSundarDhar Design of a Self- Reconfigurable Adder for Fault-Tolerant VLSI Architecture 2012 International Symposium on Electronic System Design (ISED).

    14. H.Ghasemzadeh, P.E.Gaillardon and J.Zhang , On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors 2015 IEEE Computer Society Annual Symposium on VLSI.

    15. Muhammad Ali Akbar Jeong-ALee,self-Checking Carry Select Adder with Fault Localization 2013 Euromicro Conference on Digital System Design.

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