An Overview of High Impedance Differential Scheme, Design, Protection and Simulation for a 132 KV Double Bus Bar Single Breaker System

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An Overview of High Impedance Differential Scheme, Design, Protection and Simulation for a 132 KV Double Bus Bar Single Breaker System

Mahmoud Said Mohamed Bedeir Electrical Power and Machines Department Cairo University

Giza, Egypt

Abstract This paper illustrates the common practical schematics used for high voltage bus bar protection. The schematic includes the detailed high impedance AC circuit including shunt and series resistors, nonlinear resistors (Metrosils), current transformers supervision relays circuit and overcurrent relay. The design criteria for each component that ensuring correct selectivity. The DC schematic includes the discriminative and check zones which determine the tripping criteria in which the protection will operate to protect the bus bar and how it is achieving optimal reliability. This paper demonstrates both primary and secondary circuit simulation during internal fault condition by OMICRON RelaySim Test and PSIM softwares with and without Metrosils approaches.

Keywords High impedance differential; bus bar protection; RelaySim Test; PSIM.

  1. INTRODUCTION

    Bus bars have the highest rating among all the connected electrical equipment in any electrical substation thats why they are the most vital part and if its protection fails for any reason, all the substation might be out of service or black out hence protection engineers had to find a method to protect it in proper and selective way.

    High impedance differential is one of the most economical, practical and easy to troubleshoot method for protecting EHV, HV and MV bus bars compared to other protection methods as it uses a simple circuit and one simple overcurrent protection relay for each bus bar under protection unlike Low impedance differential that uses number of slave protection relays equal to the number of feeders connected to the bus bar under protection in addition to a master relay having physical communication with the slave relays.

    In this paper we will go through the high impedance differential protection for a double bus bar and single breaker in 132 kV high voltage substation.

  2. DOUBLE BUS BAR SINGLE BREAKER SYSTEM Double bus bar and single breaker system is commonly

    used in high voltage substations either air insulated switchyard (AIS) or gas insulated switchyard (GIS) as shown in fig. 1, the used bus bar is divided into four segments (1A, 1B, 2A and 2B) connected by means of bus couplers and bus sections to provide a wide range of reliability in feeding and switching.

    Fig. 1. Double bus single breaker system

  3. HIGH IMPEDANCE DIFFERENTIAL AC SCHEMEATIC

    The primary AC circuit is simply a four segments double bus bar and some connected electrical bays through a circuit breaker and some isolators such as overhead transmission lines, underground cables, grid transformers, shunt reactors or static VAR compensators (SVC).

    As shown in fig. 2, each Bay has two CT cores assigned for bus bar protection, these CTs should have same ratio, same polarity with respect to the bus bar direction, same magnetization current Im and knee point voltage V(K) and same class. The recommended classes for high impedance relays as per IEC standard IEC 60044-6 Annex D, are class TPS and class TPX as it has low leakage flux properties.

    The secondary circuit of one CT core in a Bay will be connected directly in parallel with the corresponding Bays CT cores in same direction and polarity to result in one loop with two ends to be connected together as a ring to ensure reliability if any cut occurred in between and to be interfaced to whats called bus bar Check Zone protection panel so that any current difference between bus bar -as a single piece- inputs and outputs will flow through the loop to the check zone protection relay as per fig. 3.

    or Metrosils R(NLR), CT supervision relay (95B) and high impedance differential protection relay (87B) that will be described in details.

  4. HIGH IMPEDANCE DIFFERENTIAL CIRCUIT DESIGN

    The secondary equivalent circuit per phase is as per fig. 4.

    Where:-

    Fig. 4. High impedance secondary equivalent circuit

    Fig. 2. CT cores primary circuit connection diagram

    The secondary circuit of the other CT cores will be connected in similar way of the first core but through the isolator status to discriminate the related Bay is connected to which bus bar segment 1A, 1B, 2A or 2B and result in four ring loops to be interfaced and terminated to whats called bus bar Discriminative Zones protection panels. So that any current difference between inputs and outputs in one bus bar segment will flow through the corresponding loop to the related discriminative zone protection relay as per fig. 3.

    R(LCT): Lead resistance between healthy CTs and a saturated CT.

    R(L): Lead resistance between all CTs and the high impedance circuit.

    CT SPVN: CT supervision relay. R(NLR): Nonlinear resistor.

    R(SH): Shunt resistor. R(S): Series resistor.

    R(R): Protection relay equivalent resistor. I(FS): Secondary fault current.

    I(NLR): Metrosil leakage current. I(S): Relay Set current.

    I(SH): Current flowing in shunt resistor. V(S): Relay set voltage.

    We will design all high impedance circuit components according to data extracted from a practical case field project as per table I.

    TABLE I. Practical field data

    Parameter

    Value

    Parameter

    Value

    R(LCT)

    0.5

    R(R)

    0.05

    R(CT)

    5

    No of Bays (n)

    10

    R(L)

    5

    Km

    600/1

    Isc

    40 KA

    Kb

    2000/1

    V(K)

    500 V

    Im

    25 mA

    1. Design of Relay set voltage V(S)

      It is the voltage across the shunt resistor R(SH) at which the protective relay should operate. To design this value, we should take into our consideration that this voltage is also applied to all CT secondary circuits in parallel, so V(S) should not reach half of the knee point voltage of the current transformers V(K) to avoid CT saturation.

      V(S) < V(K)

      2

      (1)

      Fig. 3. CT cores secondary circuit connection diagram

      As shown in fig. 3, the output of each CT ring loop as a three phases is an input to a high impedance circuit which consists of series resistors R(S), shunt resistors R(SH), nonlinear resistors

      V(S) < 500 , then V(S) < 250

      2

      In case of external faults, heavy currents will flow through the

      system Bays resulting in zero current difference in CTs theoretically but in practical case there is a possibility for at least one CT to be saturated. In this case all CTs summation current will flow through the saturated CT which is specified by its secondary resistance R(CT) as it is the smallest resistance

      path. Taking into consideration the lead resistance between the healthy CTs and the saturated CT which is R(LCT) noting that the parallel resistors have a big value compared to R(CT) so it will be neglected. Since the protective relay should not respond

      R(SH) = V(S)

      I(SH)

      According to our practical data:

      0.025 150

      I(SH) = 0.6 (10 × )

      0.1 0.012

      (7)

      to external faults, so V(S) should be greater than the resulting voltage as per equation (2).

      500

      = 0.413 A

      V(S) >

      40000/p>

      V(S) > Isc × (() + ()) (2)

      Kb

      × (0.5 + 5) , then V(S) > 110

      150

      R(SH) =

      0.413

      = 363.19 365

      2000

      Where, Isc is primary maximum fault current and Kb is bus bar

      CT ratio.

      From equations (1) and (2) we can select V(S) = 150 V.

    2. Design of Relay set current I(S)

      It is the protective relay pickup current value and can be selected so that it should be higher than the relay function minimum current setting and should not be very high in order to minimize the circuit burden and hence the resistors ratings. We can use SIEMENS 7SJ64 relay for example which having minimum current setting = 0.05A, so we can select I(S) = 0.1 A.

    3. Design of Series resistors R(S)

    In case of external faults and one of the CTs is saturated, an amount of voltage will be applied to the protective relay and

    E. Design of Nonlinear resistors (Metrosils) R(NLR)

    During internal faults, heavy current will flow in the high impedance circuit which will make it subjected to a transient high voltage until the fault clearance. This high voltage can damage the whole circuit insulation thats why we need a voltage function resistors called Metrosils to suppress the high voltage by providing a low resistance path.

    First we need to check if the maximum RMS voltage during maximum fault current more than the maximum permissible voltage of the relay system then if yes we will need Metrosils. We shall select the maximum protection voltage from data sheet so that the relay system insulation can withstand as per table II (for example most LV equipment can withstand up to 1 kV).

    ( ) (8)

    ( ) (8)

    (()+())×()

    = 2 × 2 × () × (( × (() + )) )

    can easily make it operate unless a series resistors (sometimes named as stabilizing resistors) are connected so that the

    Vrms = Vmax

    2

    ()+()+()

    (9)

    protective relay shall operate only if the applied voltage is greater than V(S).

    The metrosils can be specified by the maximum continuous voltage rating (Vr) and leakage current at relay setting voltage.

    R(S) = V(S)

    I(S)

    Since V(S) = 150 V and I(S) = 0.1 A Then, R(S) = 150 = 1500

    0.1

    1. Design of Shunt resistors R(SH)

      (3)

      The maximum continuous voltage rating (Vr) should be selected more than the relay set voltage V(S)

      V(r) > V(S) (10)

      We can calculate the leakage current at relay setting voltage ( ) from the following equation:

      () 1

      Many bus bar high impedance differential protection schemes were designed without shunt resistors but it has been recorded some protective relays maloperations due to differential current produced by the following cases:

      1. In case of heavy current external faults and there is no any CT saturation but due to CT error that is not equal for all the used CTs, a differential current might be produced.

      2. In case of switching or sudden tripping of any heavy current Bay connected to the bus bar.

    That leads protection engineers to set a minimum sensitivity current limit that can operate the protective relay. The following practical equations are commonly used:

    Imp = 2 × Km (4)

    Imp = 0.5 × Kb (5)

    Where Imp is the minimum sensitivity primary current, Km is the CT ratio of the lowest load current Bay.

    We can use equations (4) and (5) to select the value whichever greater for Imp and if it is referred to the secondary circuit will be:

    Ims = Imp = (n × Ims) + I(SH) + I(S) + I(NLR)

    = ( ) (11)

    Where C = 450 for V(S) 185 V and ß 0.25.

    So in our case Vmax = 4.7 KV, Vrms = 3.3 KV, = 12 mA. Then from the metrosil manufacturer data sheet we can select the suitable model as per table II.

    TABLE II. Metrosils model selection

    F. Design of CT supervision relay

    In case of minor disturbances for high impedance secondary circuit such as wiring loose connection can introduce amount of voltage across the protective relay but still will be less than the minimum operating value V(S). A CT supervision relay is required to protect the circuit by shorting the CTs as well as

    I(SH)

    Kb

    = Ims

    (n × Ims)

    • I(S)

    • I(NLR)

    (6)

    giving alarm to the operators to investigate the problem reasons.

    Where Ims is the secondary current of Imp, Ims is the bus bar CT magnetization current at relay set voltage V(S). Noting that equation (6) should be in vectors but we used it as a magnitude for simplicity.

    We can consider that there are disturbances if the primary differential current more than or equal 125 A or a 10% of the CT ratio of the lowest load current Bay whichever is the greater.

    I(FP) 0.1 × Km (12)

    Where, I(FP) is the primary differential current due to disturbances and its minimum value is 125 A.

    Then we calculate the voltage across the CT supervision relay as following:

    VI. HIGH IMPEDANCE DIFFERENTIAL SIMULATION

    Considering a ten Bays GIS double bus bar and single breaker 132/13.8 KV substation includes four Overhead transmission lines, three grid transformers, two bus couplers and one bus section as per fig.7.

    V(CT SPVN) = I(FS) × ()+()

    ()+()+()

    So in our case V(CT SPVN) = 18 V.

    × R(SH) (13)

  5. HIGH IMPEDANCE DIFFERENTIAL DC SCHEMATIC

    Typically there are five protective relays, four relays for the discriminative zones to protect the bus bar segments (1A, 1B, 2A and 2B) and is acting as a main protection. One relay for the check zone to protect the bus bar as a single piece and is acting as a backup protection.

    Each protection has an in/out facility to put the relay in service or out of service, a CT supervision relay that could be healthy or unhealthy (operated) and a protective relay that could be in operated or not operated state.

    As per fig.5, the tripping criteria are contribution from both discriminative and check zones where the discriminative zone supplies the positive terminal of the bus bar trip relay 86BB and the check zone supplies the negative terminal.

    As per fig.6, there are five tripping cases out of total nine cases. A correct tripping case should include at least a confirmed operation from one protection either check or discriminative relays and the other protection has either a confirmed operation, out of service or CT supervision unhealthy. Bus bar should not trip for other four cases since there is no a confirmed operation.

    Fig.5.Bus bar trip relay circuit

    Fig.6.Bus bar tripping criteria

    Fig.7.System under fault simulation

    As per table I, the maximum short circuit current is 40 kA. We will simulate a three line to ground fault in Bus bar 1B using RelaySim Test and PSIM softwares.

    Fig.8 shows the system voltage and differential current at normal condition.

    Fig.9 shows the system voltage and primary and secondary differential currents at time of LLL to ground fault condition.

    Fig.8.Bus bar 1B primary differential current before fault

    Fig.9.Bus bar 1B differential current during fault

    Fig.10 shows the simulated secondary high impedance circuit updated with the data calculated from the design section.

    Fig.10.Simulated secondary high impedance circuit

    Considering the circuit without Metrosils, it is noticed that the RMS voltage across the relay as per fig.11 is around 5.8 kV which is a destructive to the relay system insulation.

    Fig.11.Secondary circuit without Metrosils analysis

    Considering the complete circuit with Metrosils of type (802/600A/S3/I) that have a maximum protection voltage Vmax = 1435 at maximum RMS fault current I(FS) = 50 A. It is noticed that the RMS voltage across the relay as per fig.11 is limited to around 405 V so that the relay system insulation can withstand.

    Fig.10.Secondary circuit with Metrosils anaysis

    1. CONCLUSION

      It has been discussed high impedance bus bar differential protection which is one of the most common, practical and economic schematics used for bus bar protection. We went through its AC and DC circuits illustration, design for each component. We compared the old circuit design without shunt resistors with the new common design with shunt resistors and how much it is important to get rid of protection maloperation. We demonstrated a ten Bays system bus bar high impedance circuit simulation with and without Metrosils to prove its merit.

    2. ACKNOWLEDGMENT

      I would like to pay my special regards to my family especially my parents, my wife and my son who encouraged me. I wish to express my deepest gratitude to all people whose assistance was a milestone in the completion of this work.

    3. REFERENCES

  1. Grid, A. (1995). Network Protection & Automation Guide Network Protection & Automation Guide Previously called Protective Relays Application Guide Network Protection & Automation Guide Network Protection & Automation Guide.

  2. Holbach, J. (2009). Comparison between high impedance and low impedance bus differential protection. 2009 Power Systems Conference: Advance Metering, Protection, Control, Communication, and Distributed Resources, PSC 2009, 164179.

  3. Cem, C. (2001). INTERNATIONALE INTERNATIONAL STANDARD CEI Part 4-2: INTERNATIONALE INTERNATIONAL STANDARD.

  4. Application Guide High Impedance Differential Protection Using SIEMENS 7SJ602 1 INTRODUCTION 2 PROCEDURE FOR PERFORMANCE CALCULATIONS. (n.d.).

  5. Testing of 600A / S1 / S256 & 600A / S3 / I / S802 Relay Metrosils. (n.d.). 802.

  6. Data, T. (n.d.). SIPROTEC Multi-Functional Protective Relay with Local Control 7SJ62/64. Control.

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