- Open Access
- Total Downloads : 423
- Authors : S. Aruna Kumari, Ravi Tejesvi Valiveti, D. Venkata Chari
- Paper ID : IJERTV3IS110910
- Volume & Issue : Volume 03, Issue 11 (November 2014)
- Published (First Online): 25-11-2014
- ISSN (Online) : 2278-0181
- Publisher Name : IJERT
- License: This work is licensed under a Creative Commons Attribution 4.0 International License
An Optimized Fully Dynamic Latched Comparator for High Speedflash and Pipeline Data Conversion Applications
S. Aruna Kumari, Ravi Tejesvi Valiveti
M.Tech-VLSI Student, Department of ECE Assistant Professor, Department of ECE Avanthi Institute of Engineering and Technology Avanthi Institute of Engineering and Technology
Visakhapatnam, India Visakhapatnam, India
D. Venkata Chari,
PG Student, Department of ECE Vizag Institute of Technology, Visakhapatnam, India
AbstractA Novel High Speed CMOS Comparator with low power dissipation, low offset and high speed is proposed. Inputs are reconfigured from typical differential pair comparator such that near equal current distribution in the input transistors can be achieved for a meta-stable point of the comparator. Restricted signal swing clock for the tail current is also used to ensure constant currents in the differential pairs. Nearly 14.6 mV offset voltage is easily achieved with the proposed structure making it favorable for flash and pipeline data conversion applications. The proposed topology is based on hysteresis using positive feedback and pre-amplifier stage, has a small power dissipation, less area, and it is shown to be very robust against transistor mismatch. Comparator structures are designed in Tanner S-edit and simulations are carried out in H-Spice to determine offset voltage, power – dissipation and speed. These are compared and the superior features of the proposed comparator are established.
KeywordsMeta-stable, Differential pair, Offset-Voltage, Hysteresis, Pre-amplifier
Over the years, development of digital integrated circuit has closely followed Moores Law. As a result, transistor size has greatly shrunk and the speed of digital circuit has been exponentially increased. There exists very high speed digital circuit with its ever growing processing power and efficiency. In real world every signal is analog in nature. So there is a need to convert the analog signal into digital signal. In order to interact analog world with digital world some sort of interface is needed for proper communication. So data conversion circuits with high speed are needed for better transmission of information. This trend puts high pressure on analog circuit designers to develop very high speed interface circuits, namely, analog to digital  and digital to analog converters. In high-speed analog-to-digital converters, comparator design  has a crucial influence on the overall performance that can be achieved.
In this paper, we present a new dynamic latched comparator which shows lower input-referred latch offset voltage  and higher load drivability than the conventional dynamic latched comparators . Even though numbers of transistors in the proposed comparator are more but overall area is small when compared to conventional dynamic latched comparators. This paper is organized as follows. Section-II provides architecture and design aspects of high speed comparators and section-III describe the conventional comparators. Section-IV describes the proposed dynamic latched comparator. Schematics and simulation results from HSPICE using 90nm PTM technology with VDD=1V and their comparisons are presented in Section-V and conclusion is drawn in Section-VI.
DESIGN ASPECTS OF HIGH SPEED COMPARATOR
The following Figure 1 illustrates the various blocks involved in the high speed comparator.
Fig.1. High Speed Comparator architecture
The pre-amplifier  is a circuit which is used to amplify the signal so that it can easily drive the load. In most latch comparator designs pre-amplifiers are also used to avoid the kickback effect  from the latch and input referred offset. This circuit is a differential amplifier with pull-up can be a resistor load or an active load. The design of the preamplifier must be done in such a manner that the desired latch input voltage is achieved in minimum time. The decision circuit is the heart of the comparator and should be capable of discriminating mV level signals. It is also called latch. The simplest form of a latch consists of two cross-coupled NMOS transistors.
The final component in comparator design is the output buffer. The main purpose of the output buffer is to convert the output of the decision circuit into a logic signal (i.e., 0 or VDD). The output buffer should accept a differential input signal. For a simple design for the output buffer, we can use the self-biased differential-amplifier.
Different Conventional comparators are Open loop and Pre-amplifier Based Latched Comparators.
Fig.2. Open Loop Comparator
Open-loop comparators , shown in Figure 2, are an operational amplifier without frequency compensation to obtain the largest possible bandwidth, hence improving its time response. Since the precise gain and linearity are of no interest in comparator design, no-compensation does not pose a problem. However, due to its limited gain- bandwidth product, open-loop comparators are too slow for many applications.
Fig.3. Pre-amplifier based latched comparator
An amplifier is employed before the latched comparator shown in figure 3, which decreases the offset voltages caused by the device mismatch as show in figure. The main advantages of the pre-amplifier based latched comparators are their high speed and low input referred latch offset voltage. In addition, by using pre-amplification stage, kickback noise can be considerably reduced and meta-stability problem also can be relaxed. Pre-amplifier based latch offer high speed and low offset while they still consume static power.
There are other types of comparators called fully dynamic latched comparators , which are Lewis-Gray Comparator, Differential pair comparator, Double-tail latch-type voltage SA , Two Stage Dynamic Comparator. Each comparator will have its own advantage and disadvantages. The various performance parameters of the comparators are compared in terms of power, size, offset voltage and delay and the superior features of the proposed comparator are established.
The proposed comparator provides better input offset characteristic and faster operation in addition to the advantages of those comparators such as less kickback noise, reduced clock load and removal of the timing requirement between clock signals over a wide common- mode and supply voltage range. The overall area is small even though number of transistors is more. It is because of widths of transistors are optimized without compromising the speed and performance of the comparator.
For its operation, during the pre-charge (or reset) phase (Clk=0V), both PMOS transistor M4 and M5 are turned on and they charge Di nodes capacitance to VDD, which turn both NMOS transistor M16 and M17 of the inverter pair on and Di nodes discharge to ground. Sequentially, PMOS transistor M10, M11, M14 and M15 are turned on and they make Out nodes and SW nodes to be charged to VDD while both NMOS transistors M12 and M13 are being off. During the evaluation (decision-making) phase (Clk=VDD), each Di node capacitance is discharged from VDD to ground in a different time rate proportionally to the magnitude of each input voltage.
Fig.4. Proposed Comparator
As a result, an input dependent differential voltage is formed between Di+ and Di- node. Once either Di+ or Di- node voltage drops down below around VDD|Vtp|, the additional inverter pairs M18/M16 and M19/M17 invert each Di node signal into the regenerated Di node signal. Then the regenerated and differentphased Di node voltages are amplified again and relayed to the output-latch stage by transistor M10M13. As the regenerated each Di node voltage is rising from 0V to VDD with a different time interval, transistor M12 and M13 turn on one after another and the final amplification is made between SW nodes before the regeneration process. Once either of SW node voltages falls below around VDDVtn, the output latch stage starts to regenerate the small voltage difference at Out nodes into a full-scale digital level.
A. Monte Carlo analysis
Monte Carlo analysis is usually utilized to model random mismatch  between different components due to process variation. Process variations may change the parameters of MOSFETs, BJTs and resistors. For accurate statistical simulation, a certain model for each of these components in a particular processing technology should be formed by the manufacturing company. These models include the distribution of different important technological parameters of each component, e.g., for a MOSFET these parameters are Vth (threshold voltage variation), W (width variation), L (length variation), tox (oxide thickness variation), etc. Since each of these variations is originated from many other independent stochastic variables, these parameters would ideally have a Gaussian distribution. Every Gaussian distribution is characterized by its mean value and the standard deviation () from that mean.
SCHEMATICS AND SIMULATION RESULTS
Fig.5. Lewis Gray Comparator (Comparator1)
Fig. 6. Latch Type Voltage SA Comparator (Comparator2)
Fig. 7. Dual-Tail Latch-Type Voltage SA Comparator (Comparator3)
Fig. 8. Two Stage Dynamic Comparator (Comparator4)
Fig. 9. Proposed Dynamic Comparator (Comparator5)
Fig. 10. Simulated Waveforms for Comparator1
Fig. 11. Simulated Waveforms for Comparator2
Fig. 14. Simulated Waveforms for Comparator5
Monte Carlo analysis is used to find the offset of comparators. For our simulation, all variations are assumed to be normally distributed about nominal values and the random mismatch in threshold voltage Vth was modeled as follows.
Fig. 12. Simulated Waveforms for Comparator3
Fig. 13. Simulated Waveforms for Comparator4
AVth is process dependent parameter and assumed to be 3mV in our mismatch analysis.
Fig.15. Monte Carlo Simulated waveform for offset calculation (Comparator5)
To compare the performances of the proposed comparator with conventional comparators, each circuit was designed using 90nm technology with = 1 , fCLK=3GHz, CLOAD=7fF, Temp=250C, and common mode voltage = 0.7 and simulated with HSPICE.
The power, delay and offset comparisons of five comparators are shown in Figures 16, 17 and 18 respectively in 90nm Technology.
Fig. 16. Power comparison
Fig. 17. Delay comparison
Fig. 18. Offset comparison
A novel high-speed, low power and low-offset dynamic latch type comparator method is presented in this work. The proposed design uses isolated differential stage and latch stage which leads to low kickback noise and also it uses the preamplifier stage before the latch stage, which reduces the offset voltage by its gain. The Monte- Carlo simulation results clearly reveal that the dynamic latch comparator is able to switch properly with different input stepping sizes. The comparison study shows that the novel design is able to operate at a higher clock frequency of 3GHz with less offset voltage, low power and propagation delay in 1V supply voltage, which is better than other dynamic latched comparators.
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S. ARUNA KUMARI received her B.Tech degree from Baba Institute of Technology and Management in the year 2012 and presently pursuing M.Tech degree in Avanthi Institute of Engineering and Technology. Her
research activities are related to Low power VLSI Design.
RAVI TEJESVI VALIVETI received
his B.Tech degree from St.Theressa Institute of Engineering and
Technology in the year 2010 and received M.Tech degree from St.Theressa Institute of Engineering and Technology in the year 2013. He is working as an Assistant Professor in the Department of Electronics and Communication Engineering at Avanthi Institute of Engineering and Technology.
D. VENKATA CHARI received his B.Tech degree from Vizag Institute of Technology in the year 2012 and presently pursuing M.Tech degree in Vizag Institute of Technology. His research activities are related to Low power VLSI Design.