- Open Access
- Total Downloads : 528
- Authors : Nikhil A. Bobade, Prof. Jayshree D. Dhande, Dr. Mahendra A. Gaikwad
- Paper ID : IJERTV3IS10889
- Volume & Issue : Volume 03, Issue 01 (January 2014)
- Published (First Online): 28-01-2014
- ISSN (Online) : 2278-0181
- Publisher Name : IJERT
- License: This work is licensed under a Creative Commons Attribution 4.0 International License
A Review : Design of Successive Approximation Analog to Digital Converter
Nikhil A. Bobade
Prof. Jayshree D. Dhande
Dr. Mahendra A. Gaikwad
Dept. of Electronics,
Dept. of Electro. and Telecomm
Dept .of Electro. and Telecomm
This paper presents the analog to digital converter (ADC) for low power applications, so selection of right architecture is very crucial. We have chosen successive approximation Analog to Digital Converter because of their compact circuitry as compared with the Flash ADC which makes this SAR ADC inexpensive. Day by day number of applications are built on the basis of efficient power consumption with moderate sampling rate. This SAR ADC will be useful for high speed with medium resolution and low power consumption.
Keywords: Analog to digital converter, Low power, Resolution, Successive Approximation Register (SAR), Sampling Rate.
In many mixed-signal systems, Analog-to- Digital Converters (ADC) are required for interfacing analog signals to digital circuits . ADC provides connection between hardware systems and digital signal processing systems. Sigma Delta ADC architectures are very useful for lower sampling rate and higher resolution (approximately 12-24 bits). The common applications for Sigma-delta ADC architecture are found in voice band, audio and industrial measurements . Fig.1 shows Successive Approximation (SAR) is very suitable for data acquisition; it has resolutions ranging from 8 bits to 16 bits and sampling rates ranging from 50 KHz to 100 MHz. The most effective way to create a Giga rate application with 8 to 16 bit resolution is the pipeline ADC architecture. In the past few years, demand of SAR ADC is increased because more and more applications are built with very stringent requirements on power consumption. For electronic systems, such as wireless systems or portable devices, the power consumption is one of the most critical factors.
Figure 1. Sampling rate versus bit resolution of different ADCs
SAR ADC is known for its simple structure, thus consuming less power and saving more die size.SAR ADC also use in Ultra Wide Band(UWB) radio technology. Low-resolution is the main requirement of UWB receivers but high- speed analog-to-digital converters (ADCs), in the range of 45 bits. Pipelined ADCs are mainly used for high-speed, medium-resolution applications. They can provide one conversion per clock period throughput and only a linear scaling in complexity with resolution; however they rely on operational amplifiers at the heart of the multiplying digital-to- analog converter (MDAC) in each pipelined stage. Because it must be closed loop stable, this amplifier typically uses one or two high gain stages . Unfortunately, in deep nanometer CMOS, the achievable gain per stage is limited because short- channel effects lower gm r0 for a single transistor, and reduced voltage supplies restrict circuit techniques such as cascoding. Thus, there are certain difficulties for continued scaling of pipelined ADCs. Thus SAR ADCs are commonly used in biomedical acquisition systems due to their low power consumption, moderate sampling rate and simplicity, particularly for simple analog sub- circuits. SAR ADC consists of sample and hold circuit, a comparator, successive approximation register, control logic and DAC circuits. Control logic, comparator, and DAC network are the primary sources of power dissipation. Technology
scaling improves speed and minimizes power dissipation.
ALGN Aditya et.al  presents Low power Successive Approximation ADC for MAVS. Here MAVs is a Micro Air Vehicle system. In communication subsystems such as Micro air vehicles MAV's, it becomes mandatory to design the circuits with low power and low voltage to enhance the system by means of long sustainability and less power consumption with maintenance free operation, especially in the circuits like Analog to Digital Converters (ADCs). In chemical cloud different types of gases are present in that mainly carbon monoxide which are very harmful. MAV is consisting of a sensor it can detect the toxic gases which are released from vehicle. Here sensor signals are analog signals need to convert into digital signals for visualization with the help of Successive Approximation ADC. The analog input frequency is 75MHz and oversampling conversion frequency is 750MHz with 27.4mW low power design is achieved with this technique. This is implemented in 180nm technology .
Brian P. Ginsburg et.al  proposed ADC for ULTRA WIDEBAND (UWB) radio technology. The Ultra Wide Band radio technology is an emerging technology For very high data rate and Short Distance Wireless communication. UWB receivers require high speed but low resolution analog to digital converter in the range of 4-5 bits. The time-interleaved successive approximation register (SAR) architecture has been chosen due to its simplicity versus flash and its amenability to scaled technologies versus pipelined, which relies on operational amplifiers. In this ADC, there is use of split capacitor array DAC which is used For Increasing the speed and For Reduces the switching energy. This ADC consumes 6mw from 1.2 V supply. This is implemented in 65 nm technology .
Siamak Mortezapour et.al  presents ADC designed for low-power, medium-quality applications such as data acquisition. The requirement is usually to integrate these ADCs with digital signal processors (DSPs) in a low-cost CMOS technology. ADCs that are integrated with
a DSP are required to operate in the same range of supply voltage. However, designing an ADC to operate at such a low supply voltage presents a great challenge, which comes from the fact that the threshold voltages of MOSFET devices are relatively high for the given supply voltage ranges even for future CMOS processes. To address this challenge, different techniques have been used to realize ADCs including the use of specialized process that provides low-threshold devices, bootstrap techniques, and switched-op-amp techniques. This ADC consumes 0.34 mW from 1V supply. This technique is implemented in 120 nm process .
Young-Kyun Cho et.al  presents ADC for high speed wire line and wireless communication system. In these applications, low-power and small-area ADCs requiring conversion rates higher than 60 MS/s and a resolution in the range of 79 bits are considered an important building block. Among many ADC architectures, successive approximation register (SAR) ADCs have proven to be very efficient for meeting the above requirement of high speed, medium resolution, and low power consumption. In this ADC , a comparator with offset cancellation and uses digital calibration for error correction. This ADC consumes 3.4mW with the reference 1.0V supply. This ADC is implemented in 65-nm CMOS technology with area of 0.068mm^2.
Pieter J. A. Harpe et.al  presents ADC for upcoming low energy radios in the ISM (industrial, scientific and medical) radio bands such as low- energy Bluetooth or IEEE 802.15.6 for body-area networks. The successive approximation architecture (SAR) is selected in this work because of the excellent power efficiency The use of simple modulation schemes like OOK, moderate resolutions (e.g. 4 bit up to 8 bit) are sufficient. Data rates are strongly application dependent, but are typically expected in the rage of several KS/s (e.g. medical sensor applications like ECG monitoring) up to several MS/s (e.g. audio streaming). This work proposes an architecture that achieves excellent power-efficiency for an 8 bit ADC using sample rates from 1 KS/s up to 10 MS/s. Here By using dedicated 0.5 fF capacitors, asynchronous dynamic logic and a low-complexity design, an energy efficiency of 12fJ/conversion- step could be achieved at 10MS/s. Because of the fully dynamic design and a low leakage level of only 6 nW, the excellent efficiency is maintained down to the kS/s range .
Guan-Ying Huang et.al  presents an energy efficient successive-approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. In the last few years, there has been a growing interest in the design of wireless sensing device for portable, wearable or implantable biomedical applications. These sensing devices are generally used for detecting and monitoring biomedical signals such as electrocardiographic (ECG), electroencephalography (EEG), and electromyography (EMG). Most biomedical signals are often very slow and exhibit limited dynamic range. A typical biomedical sensor interface consists of a band-pass filter, a low-noise amplifier and an analog-to-digital converter (ADC). The digitalization of the sensed biomedical signals is usually performed by ADCs with moderate resolution (812 bits) and sampling rate (11000 kS/s). This ADC fabricated in 0.18-m 1P6M CMOS technology having 0.6-V power supply voltage with sampling rate 200-kS/s, the ADC achieves a signal-to-noise and distortion ratio of 57.97 dB and consumes 1.04 W, resulting in a figure of merit of 8.03fJ/conversion-step. The ADC core occupies an active area of only 0.082sq.mm .
Successive Approximation Analog to Digital Converter has been implemented with medium bit resolution in particular nanometer technology having moderate sampling rate. In order to implement SAR ADC with efficient power consumption we have to use minimum nanometer technology. This SAR ADC having Resolution of 8 bit with sampling rate in Mega Samples per Second in reduction in its nanometer technology. Such compact low power SAR ADC design provides less chip size also minimization of power consumption. Also to achieve low power consumption, an energy saving switching sequence technique can be used in the designing of the DAC architecture. Due to Larger capacitor ratio from MSB capacitor to LSB capacitor, conventional binary weighted capacitor array has limitation in higher bit resolution. Hence to eliminate this problem one technique can be applied known as minimum capacitor technique. Fig.2 shows general block diagram of successive approximation registers having 8 bit DAC . This Proposed SAR ADC will be designed in Tanner Tool V15.0.Performance evaluation will
based on the implementation results obtained through this tool.
Figure 2. Block Diagram of SAR ADC
A SAR ADC is suitable for medium bit resolution with higher sampling rate from kS/s to MS/s. The SAR ADC has compact design compare to flash ADC, which makes SAR ADC inexpensive. In future, SAR ADC using minimum capacitor technique will be energy efficient and cost-effective. Proposed work will achieve efficient successive approximation analog to digital converter having medium bit resolution of the data convertor with efficient power consumption and moderate sampling rate.
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