DOI : 10.17577/IJERTCONV2IS01030

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In the last years strong efforts were made to miniaturize microelectronic systems. Chip scale packages, flip chips and multichip modules are now commonly used in a great variety of products. Future microelectronic applications require significantly more complex devices with increased functionality and performance. Due to added device content, chip area will also increase. Performance, multi-functionality and reliability of microelectronic systems will be limited mainly by the wiring between the subsystems (so called "wiring crisis"). 3D System Integration provides a base to overcome these drawbacks.3D integrated systems show reduced chip areas and enable optimized partitioning, both which decrease the fabrication cost of the system. An additional benefit is the enabling of minimal interconnection lengths and the elimination of speed- limiting inter-chip interconnects. 3D concepts which take advantage of wafer level processing to avoid increasing package sizes and expensive single component assembling processes have the potential to integrate passive devices resistors, inductors and capacitors into the manufacturing system and provide full advantage for system performance.


The ITRS roadmap predicts an increasing demand for systems-on-a-chip (SoC) Conventional fabrication is based on embedded technologies which are cost intensive. A new low cost fabrication approach for vertical system integration is introduced. The wafer-level 3D SoC technology, optimized to the capability for chip- to-wafer stacking has the potential to replace embedded technologies based on monolithic integration.Several companies and research institutes all over the world are currently working on the development of 3D system integration technologies. Industrial users are for example working in the areas of high-density memories, high performance processors, real time image processing and aerospace applications. Besides approaches based on fabrication of multiple device layers using recrystallization or epitaxial growth of Si,the large spectrum of technological concepts can be classified in three categories: a) Stacking of packages, b) Stacking of chips and c) Vertical system integration by wafer stacking or chip-to-wafer stacking, respectively.


  1. Stacking of Packages:

    A number of concepts that exceed conventional multichip module (MCM) technology are based on stacking of packaged devices and their interconnection via side-wall contacts. In the framework of ESPRIT project 6490 the so-called vertical multichip-module concept MCM-V was developed by NMRC.Besides the standard application of memory stacks, the MCM-V was used to realize image processing systems (gray scale camera, A/D converter and processors). A well established way of realizing stacked packages, mainly for MEMS applications, is using TB-BGA (Top Bottom Ball Grid Array) modules. FR4 casings are made up of basically three parts: a top, a bottom and a frame. The upper side of the top and the backside of the bottom are equipped with defined interfaces for data transmission. A bus system has been integrated into the frame to transfer data from module to module. Top, bottom and frame are soldered or mounted together by a conductive adhesive. The standardized interfaces according to VDMA standards sheet 66305 ensure that even microsystems from different manufacturers are compatible with each other. Berlin has introduced the so-called chip-in- polymer technology (CIP) [5]. CIP offers the way to 3D system integration by embedding very thin components into build-up layers of printed circuit boards (PCB´s). Thin chips of about 50 m are die bonded to a FR4 panel. They are embedded in a liquid epoxy dielectric by spin coating or by vacuum lamination of a dielectric layer. Vias to the bond pads of the chip and to the board are opened by photolithography or, in case of the laminate, by a laser. Finally the chips are electrically connected by fully-additive electroless Cu deposition of conductor lines. Integrated resistors are obtained by electroless deposition of a thin, highly-resistive NiP layer.CIP combines of a high integration density with the advantages of established, cost-effective PCB materials and processes. Extreme thin stackable packages can be manufactured on large panels.The approaches outlined above are assembly technologies at chip-level with a small number of vertical contacts and comparatively high fabrication cost (single chip processing). For this reason Irvine Sensors was coming up with its neo-stacking technology. To start with, a compound matrix with the size of a standard wafer is generated, into which thinned chips are embedded. This so-called neo-wafer can be processed using wafer technology.

  2. Stacking of Chips:

    3D integration technologies based on stacking of bare chips are established in production lines of several companies worldwide. Applications are DRAM, SRAM and Flash EPROM stacks for mobile applications. Interconnections of the stacked chips using wire bonding are used by e. g. Hitachi, Sharp and Amkor. Intel´s Ultra

    Thin Stacked Chip Scale Packaging technology allows CSPs with up to 5 dice providing a low package profile of 0.8 – 1.2 mm.Other chip stacking approaches are using flip chip technique on silicon or flex interposer or combined techniques with flip chip and wire bond interconnects.A BGA (FR 4 substrate) can have a flip chip mounted microcontroller on a silicon chip with redistributed IO-pads. The interconnects from the interposer to the substrate are wire bonds.A so called face-down wafer level circuit integration technique is based on an extension of a standard redistribution technology for wafer-level-CSPs. In the approach of Fraunhofer IZM a base chip at wafer level will be used as an active substrate for smaller and thinner ICs. These thinned active components are assembled in flip chip fashion on the base IC using solder bumps. Large solder balls (> 300 m) on the base chip can be utilized for the interconnect to the next package level. This technology uses thin film techniques to reroute the peripheral I/Os to an array of under bump metallization (UBM) pads. A low electrical resistivity of the rewiring metallization is achieved by electroplating copper. A low-k photo- definable layer (BCB) is used as the dielectric layer. For performing an efficient 3D system integration it is necessary to consider the passive components of a system as well. In addition to size and cost saving the integration of passives leads to advantages in reliability and electrical behaviour. Wafer level processing enables the integration of resistors, inductors and capacitors into the redistribution process as well.A different approach, the thin chip integration concept (TCI), can be used to avoid the flip chip assembly process for the module. Key element of this technology are extremely thin completely processed wafers and chips. In contrast to existing packaging techniques the TCI concept uses 20 m thin chips mounted on a base chip by adhesive or soldering. This technique offers excellent electrical properties of the wiring system and the interconnection of the active and passive devices. The signal transmission time for high speed memory modules will be reduced compared to single chip packages.The process for TCI modules starts up with one type of bottom wafer carrying large base chips. The completely processed device wafers for the top IC have to be mounted on a carrier substrate by a

    stacking approach is devloped by the Tohoku University in cooperation with CREST: by wafer bonding of a thinned top wafer to a bottom wafer, using doped poly- silicon filled inter-chip vias and Au/In micro bumps as vertical interconnects, they demonstrated the realization and basic operation of a 3D microprocessor consisting of three circuit layers. However, the described high-density 3D integration technology is based on the generation of buried interconnects which requires essential interventions to the basic IC process technology, thus considerably increasing the fabrication costs. The Japanese Association of Super-Advanced Electronics Technologies (ASET) is currently working on wafer- level stacking concepts without interfering the basic IC process. One of their project targets is a super-high density 3D LSI chip integration technology for interconnecting more than five device layers by electroplated via holes through 50 – 70 m thin device substrates (20 m pitch). The results they are presenting are very promising. Due to the comparatively large lateral size of the etched inter-chip vias (typically 10 – 20 m), they are metallized by electroplating of copper. The challenge is to fill these very deep inter-chip vias without voids. For this reason high conformal e. g. time- modulated Cu plating techniques have to be applied with corresponding long deposition times (> 1 hour), which would result in rather high fabrication cost. The ICV concept in principle is suitable for both, wafer- stacking and chip-to-wafer-stacking for vertical system integration. The wafer-stacking approach is well suited for 3D integration of devices with nearly identical chip areas. Prior to wafer stacking inter-chip vias (ICVs) with typically 1 – 3 m diameter are prepared on the top wafer. The high aspect ratio ICVs are etched through all dielectric layers and typically 12 m deep into the silicon. The wafer is then temporarily bonded onto a handling substrate by using a glue polymer and thinned with high uniformity until the ICVs are opened from the rear (remaining silicon thickness approximately 10 m). After optical alignment of the stabilized top wafer versus a polyimide coated bottom wafer, the durable polyimide bond is established at approximately 400 °C and the handling substrate is removed. Now the inter-chip vias are opened to the bottom wafers metallization, laterally

    reversible adhesive bond and undergo a backside

    thinning process until the thinned wafers show a

    isolated with highly conformal O


    /TEOS and finally

    remaining thickness of approximately 20 m. The thinned chips are mounted on the active base wafer (bottom wafer) and covered by a photosensitive dielectric layer . BCB as dielectric layer offers excellent electrical properties, high temperature stability, very low water up- take with a medium curing temperature. A thin film redistribution process (Cu) is used to interconnect the top and carrier circuits. The wiring system is covered by a solder-mask (Photo-BCB). The similar process sequence can be used to integrate a second active device on top of

    refilled with TiN/W CVD. Subsequently, a tungsten etch back process is applied for W-plug formation. The lateral electrical connection of the metallized inter-chip via with the metal level of the top wafer is done by opening contact windows on the top wafer followed by a standard Al metallization and passivation. Finally, the bond pads are opened and the 3D integrated device stacks can be tested, diced and packaged by use of standard procedures.Wafer stacks fabricated according to the ICV technology show a very high vertical interconnect


    the base wafer. Finally the deposition of an under bump

    density of some 100 000 cm

    with low contact resistance

    metallization and a solder bump deposition completes the manufacturing of the TCI module.

  3. Vertical System Integration:

The principle of vertical system integration is characterized by very high density vertical inter-chip wiring of stacked devices. Thinned device substrates (wafers or dice, respectively) are stacked by aligned bonding and electrically interconnected by free positioned inter-chip vias. A corresponding wafer

inter-chip vias. Reliability tests proved that the yield and functionality of nonvolatile memories basically are not affected by the corresponding thinning and bonding processes. Because the ICV technology is marked by the use of CMOS-compatible materials and process steps exclusively, it allows for fabrication of 3D SoC´s in standard semiconductor production lines.

Vertical system integration in general is based on thinning, adjusted bonding and vertical metallization of completely processed device substrates by inter-chip vias

placed at arbitrary locations. For wafer stacking approaches, the step raster on the device wafers must be chosen identically. This is easily fulfilled for 3D integration of devices of the same kind (e.g. memories) but in the general case of different device areas, the handicap of processing with identical step raster would result in active silicon loss and in consequence increase the fabrication cost per die. In most cases this restriction is even more serious than the yield loss by stacking a non functional die to a good die. For chip-to-wafer stacking approaches the starting materials are completely processed wafers, too. After wafer-level testing, thinning and separation, known good dice of the top wafer are aligned bonded to the known good dice of a bottom wafer. This process step represents the only one on chip- level within the total vertical system integration sequence. The subsequent processing for vertical metallization is on wafer-scale again. In the case of the above described ICV technology based on polyimide bonding the process flow for chip-to-wafer is more complex and therefore cost-intensive mainly because of the need for lithography steps on a bottom wafer with mounted dice.In consequence we are working on the development of a new vertical system integration technology with no need for additional process steps on stack level. The so-called ICV-SLID concept is based on the bonding of top chips to a bottom wafer by very thin Cu/Sn pads (thickness approximately 8 m) which provide both, the electrical and the mechanical interconnect. The new approach combines the advantages of the well-established ICV process and the solid-liquid- interdiffusion technique which is already successfully applied for face-to-face die stacking [9]. The ICV-SLID concept is a non-flip concept. The top surface of the chip to be added is the top surface after stacking it to the substrate. The inter-chip vias are fully processed etched and metallized as well prior to the thinning sequence, with the advantage that the later stacking of the separated known good dice to the bottom device wafer is the final step of the 3D integration process flow. As a fully modular concept, it allows the formation of multiple device stacks.COSeveral outstanding technology concepts for 3D integration are currently in development, a few of them are already in production. Successful market entry will be determined by the performance improvement achieved and the profitability in relation to the total system cost. Manufacturing technologies largely relying on wafer fabrication processes show a comparatively favorable cost structure. Wafer yield and chip area issues may speak against wafer stacking concepts. In consequence, chip-to-wafer technologies mainly based on wafer-level processes utilizing known good dice only, will be of advantage. A corresponding new approach for vertical system integration, optimized to the capability for chip-to-wafer stacking, is introduced and discussed. The so-called ICV-SLID technology is based on adjusted bonding and vertical metallization of completely processed device substrates without interfering the basic IC process. The proposed wafer- level 3D integration concept has the potential for low cost fabrication of high-performance 3D-SoCs and is well suited asa replacement for embedded technologies.


1.H. Yonemura, M. Tomisaka, M. Hoshino, K. Takahashi, H. Kadota, Proc. Advanced Metallization Conference 2002 (AMC 2002), edited by B.M. Melnick,

T.S. Cale, S. Zaima, T. Ohba (Mater. Res. Soc. Proc. V- 18, Warrendale)

2.Peter Ramm,Armin Klumpp, Reinhard Merkel, Josef


Weber, Robertwieland, Technical University of Berlin Gustav-Meyer-Allee 25, 13355 Berlin, Germany

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