Implementation of an Alternative High Performance Flip Flop to JK Flip Flop

Computer performance is primarily affected by the processor and memory. If either one reaches its limits, the performance of the whole system degrades. As semiconductor technology advances, the performance gap between processor and memory has become one of the major issues in computer design. This situation causes a growing gap between processor and memory in the performance. Hence the design of an efficient and high performance memory element known as Flip-Flop Extension is of crucial importance in computer design. The analysis of the existing structures is necessary when the requirement of the Flip-Flop is for low-power and highspeed digital applications. This study is dedicated to the investigation of the existing conventional memory elements, the SET /RESET (SR) and JUMP-KEY (JK) Flip Flops performance and the result is used to evaluate the design of an alternative Flip Flop known as Flip Flop Extension. It is evidence from the analysis, that the JK-FF Extension at 87.5% has one gate less than the conventional SR & JK-FFs. This is a great advantage in performance because fewer gates enhance performance in which numbers of gate/ transistors represent hardware cost.


INTRODUCTION
Flip-Flops are digital circuits with two stable, selfmaintaining states that are used as storage/ memory elements such as Random Access Memory (RAM), Caches Memory and Read Only Memory (ROM). They are also very useful in the following electronic digital devices design; Sequence Detector, Data Synchronizer, Frequency Divider, Registers (data transfer), Counters and Registers in Central Processing Unit (CPU) for data transfer. They are derived from Sequential Logic Circuits which are the main electronics circuits that make the development of computers possible. The ability of computer systems to operate without the continuous human intervention is solely achieved through sequential logic circuits, the building blocks of Flip Flops [1].

MOTIVATION FOR THE STUDY
It has been observed that computer performance is primarily affected by the processor and memory. If either one reaches its limits (which may initially be the memory), the performance of the whole system degrades. As semiconductor technology advances, the performance gap between processor -the Central Processing Unit (CPU) and main memory -the Random Access Memory (RAM) has become one of the major issues in computer design. In the past 45 years, an exponential rate of improvement has been witnessed in semiconductor technology. The processor performance increases at a rate of 60% per year while the memory performance increases just 10% per year [2; 3]. This situation causes a 50% growing gap between processor and memory in the performance as depicted in Figure 1.1. If memory fails to keep pace with the processor's constant demands, the processor stalls in a wait state, and valuable processing time is lost. This imbalance has become one major bottleneck in further improving the computer performance. One reason memory system performance has consistently lagged processor performance is that memory systems typically consist of one or more chips that are designed and manufactured separately from the processor, and the performance of the interconnected multi-chip memory system is difficult to scale to achieve higher data-rate and lower access latency. Memory system data-rates are increasing with each new generation of memory devices at the rate of 100% every three years, and memory row cycle times are decreasing at a rate of approximately 7% per year [4]. The collective trends are increasing the ratio of row cycle times to the duration of data bursts on the data bus. This is why it is imperative to critically evaluate the existing conventional JK-FF and the need to bridge the speed gap between memory and processor by enhancing the memory speed through logical modification frameworks of the conventional JK-FF which utilizes 75% out of the 100% of its' states.
Put equation (1c) into (1a), we have   Table 1.2, and are stated according to our adopted convention as follows:   Note that the positive logic design configuration is actually the complement of the negative logic design configuration; which shows that either design will produce the same performance.           Table 1.5 is the summary of the various Flip Flops design with the aim of verifying their gate structures and numbers.

CONCLUSIONS
Previous study revealed that very little research have been carried out on Flip Flops comparative analysis in the 100%, 87.5% and 75% active states utilization on digital device applications. In this paper, a new approach of designing memory element (Flip Flop) with its active states utilization of 87.5% and or 100% as against the conventional Flip Flops at 50% and 75% active states utilization which will enhance memory performance have been developed. This is evidence in section 7 and 8 where the Flip Flop Extensions at 87.5% active states utilization is designed with one gate less than the conventional JK-Flip Flop. The uniqueness of this study is that computer memory speed performance can be enhanced through conventional JK-FF modification just as it is currently being done with its processor counterpart. This is a great advantage in performance over the conventional Flip Flops because fewer gates enhance performance (i.e., gate delay represents performance). The 87.5% Flip Flop extension memory cell is also portable (less transistors) and cheaper because it requires fewer transistors as against the conventional Flip Flops. An important issue in digital device design is that numbers of transistors represent hardware cost because in essence, maximizing performance and minimising cost in digital devices are part of the factors in seeking alternative design on more efficient and effective Flip flops.
Efforts should be geared towards verifying the effectiveness and efficiency of these newly design Flip Flops Extension over the existing conventional Flip Flops.