High Speed Truncation- Error -Tolerant Adder

High Speed Truncation- Error -Tolerant Adder
Authors : Ratna Deepthi Kethineni
Publication Date: 03-08-2012


Author(s):  Ratna Deepthi Kethineni

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Vol.1 - Issue 5 (July - 2012)

e-ISSN:   2278-0181


Abstract: In this study, we had proposed architecture for high speed Truncation Adder Algorithm. In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain more than 74% improvement. One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors. The modifications to the conventional shift and add multiplier includes introduction of modified error tolerant technique for addition and enabling of adder cell by current multiplication bit of the multiplier constant.


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