Efficient 8x8 Multiplier Based On Gate Diffusion Input Technique

Efficient 8x8 Multiplier Based On Gate Diffusion Input Technique
Authors : Narendra Lakhani, Kiran Gupta
Publication Date: 26-07-2013


Author(s):  Narendra Lakhani, Kiran Gupta

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Vol.2 - Issue 7 (July - 2013)

e-ISSN:   2278-0181


Power consumption has become a critical concern in today¡Çs VLSI system design. The growing market for fast DSP and multi-core processors has created a demand for low power, area efficient multipliers. A Wallace tree multiplier is an improved version of tree based multiplier architecture. It uses carry save addition algorithm to reduce the latency. This paper aims at additional reduction of power and area using compressors based on Gate Diffusion Input Technique. Full adder designed by GDI technique use only 10 transistors and it is used in compressors. In this paper Wallace tree is constructed using 4:3 and 5:2 compressors. Therefore, minimizing the transistor count make it low power and area efficient.


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