Author(s): Narendra Lakhani, Kiran Gupta
Published in: International Journal of Engineering Research & Technology
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Volume/Issue: Vol.2 - Issue 7 (July - 2013)
Power consumption has become a critical concern in today¡Çs VLSI system design. The growing market for fast DSP and multi-core processors has created a demand for low power, area efficient multipliers. A Wallace tree multiplier is an improved version of tree based multiplier architecture. It uses carry save addition algorithm to reduce the latency. This paper aims at additional reduction of power and area using compressors based on Gate Diffusion Input Technique. Full adder designed by GDI technique use only 10 transistors and it is used in compressors. In this paper Wallace tree is constructed using 4:3 and 5:2 compressors. Therefore, minimizing the transistor count make it low power and area efficient.
Number of Citations for this article: Data not Available
7 Paper(s) Found related to your topic: