IJERT-EMS
IJERT-EMS

Design And Synthesis Of 32 BIT ALU Using Xilinx ISE V9.1i


Design And Synthesis Of 32 BIT ALU Using Xilinx ISE V9.1i
Authors : Kaushik Chandra Deva Sarma, Amlan Deep Borah, Lalan Kumar Mishra
Publication Date: 16-05-2013

Authors

Author(s):  Kaushik Chandra Deva Sarma, Amlan Deep Borah, Lalan Kumar Mishra

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Vol.2 - Issue 5 (May - 2013)

e-ISSN:   2278-0181

Abstract

The paper presents Design and Synthesis of 32- BIT Arithmetic Logic Unit (ALU). The design has been implemented using VHDL Xilinx Synthesis tool ISE 9.1i and targeted for Spartan device. ALU is designed to perform Arithmetic operations such as addition, subtraction, overflow; logical operations such as AND, OR, XOR, XNOR and NOT operations, Parity check, 1”Ēs and 2”Ēs complement operations, compare, etc. The ALU is a fundamental building block of the Central Processing Unit (CPU) of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers. The processors found inside modern CPUs and Graphics Processing Units (GPUs) accommodate very powerful and very complex ALUs; a single component may contain a number of ALUs. Flags like Zero, Carry and Odd Parity show the status of each Flag for result of the ALU”Ēs operation in each clock cycle. Zero Counter counts number of zeros in the result. The modern ALU must be capable to perform all the binary arithmetic and logical operations to meet the requirements of modern VLSI industry. So, the paper is a forward step to design the ALU and meets the demand of present FPGA based technology. The paper presents a number of new operations (Parity,Overflow,Zero,Zero counter etc.) that an ALU can perform than so far designed ALU in VHDL.

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