IJERT-EMS
IJERT-EMS

Design of Low Voltage High Speed Operational Amplifier for Pipelined ADC in 90 nm Standard CMOS Process


Design of Low Voltage High Speed Operational Amplifier for Pipelined ADC in 90 nm Standard CMOS Process
Authors : Shri Kant, O. P. Sahu
Publication Date: 30-06-2012

Authors

Author(s):  Shri Kant, O. P. Sahu

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Vol.1 - Issue 4 (June- 2012)

e-ISSN:   2278-0181

Abstract

This paper presents the low voltage high speed operational amplifier for pipelined ADC in 90nm standard CMOS process. The designed Opamp can operate at a supply voltage of 1V and provides a gain of 81.11 dB, unity gain frequency of 485.2MHz and slew rate of 239.62V/?s with 12ns settling time. The schematic is captured using Cadence Virtuoso and simulated using Cadence Spectre simulator in 90nm CMOS technology. The designed Opamp satisfies the requirements of a pipelined ADC and can be utilized in the S/H block of pipelined ADC.

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