A New Topology For A Single Phase 21 Level Multi Level Inverter Using Reduced Number Of Switches

A New Topology For A Single Phase 21 Level Multi Level Inverter Using Reduced Number Of Switches
Authors : Jithin.J.I, A.Benuel Sathish Raj
Publication Date: 28-02-2013


Author(s):  Jithin.J.I, A.Benuel Sathish Raj

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Vol.2 - Issue 2 (February - 2013)

e-ISSN:   2278-0181


Abstract?The proposed topology significantly reduces the number of dc voltage sources, switches, IGBTs, and power diodes as the number of output voltage levels increases. To synthesize maximum levels at the output voltage, the proposed topology is optimized for various objectives, such as the minimization of the number of switches, gate driver circuits and capacitors, and blocking voltage on switches. This new type of converter is suitable for high voltage and high power applications. This multilevel inverter has ability to synthesize waveforms with better harmonics spectrum. The power loss in the circuit is less due to less number of switches. There are numerous topologies has been introduced and widely studied for utility and drive application. In this work a study of 21-level inverter using less number of switches as compare to the technologies previously developed. MATLAB software is used for simulate the 11-level inverter. Multilevel inverter is fulfilling the requirement of heavy-duty electric and hybrid-electric vehicles (EH”Ēs) of large electric drives (>250KW). When we increases the level of inverter then we gets the high output voltage and the stress of each switch is also reduces means each switches faces low value of dv/dt. The output waveform of multilevel inverter follows the sinusoidal waveform hence the harmonic contents are less. Therefore there is small loss of energy in the circuit if we study the cascaded multilevel inverter. It exhibits several attractive features such as simple circuit layout, less components counts, modular in structure and avoid unbalance capacitor voltage problem. However as the number of output level increases, the circuit becomes bulky due to the increase in the number of power devices. In this project, it is proposed to employ a new technique to obtain a multilevel output using less number of power semiconductor switches.


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