IJERT-EMS
IJERT-EMS

Fault Detection for ISCAS 89 S-27 Benchmark Circuit Using Low Power Lt-RTPG


Fault Detection for ISCAS 89 S-27 Benchmark Circuit Using Low Power Lt-RTPG
Authors : N. Subhramanyam, Ambavaram Poli Reddy, J. Rajpraveen
Publication Date: 30-01-2013

Authors

Author(s):  N. Subhramanyam, Ambavaram Poli Reddy, J. Rajpraveen

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Vol.2 - Issue 1 (January - 2013)

e-ISSN:   2278-0181

Abstract

In this project test patterns generated by the Low- transition random pattern generator (LT-RTPG) detect Easy-to-detect faults. This LT-RTPGs are normally used in Built In Self Tests (BIST). This project also presents a novel low-transition linear feedback shift register (LFSR) that is based on some new observations about the Output sequence of a conventional LFSR. The proposed design, called Bit-swapping LFSR (BS-LFSR), is composed of an LFSR and a 2 1 Multiplexer. When used to generate test patterns for scan-based built-in self- tests, it reduces the number of transitions that occur at the scan-chain Input during scan shift operation by 50% when compared to those patterns produced by a conventional LFSR. The proposed LT-RTPG can significantly reduce switching activity during BIST. These techniques have a substantial effect on average and peak-power reductions with negligible effect on fault coverage or test application time. Experimental results on ISCAS89 S-27 benchmark circuits show up to 65% and 55% reductions in average and peak power, respectively.

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