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FPGA Implementation of Orthogonal Code Convolution for Efficient Digital Communication


FPGA Implementation of Orthogonal Code Convolution for Efficient  Digital Communication
Authors : Raghvendra Dubey, P. Lakshmi Sarojini
Publication Date: 29-12-2012

Authors

Author(s):  Raghvendra Dubey, P. Lakshmi Sarojini

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Vol.1 - Issue 10 (December - 2012)

e-ISSN:   2278-0181

Abstract

In digital communication system, convolution coding is preferred for the channel coding as it facilitates a better error correction as comparison to block coding which does not require memory. Among other techniques such as Cyclic Redundancy and Solomon Codes; orthogonal coding is one of the codes which can detect errors and correct corrupted data in an efficient way. In this paper, FPGA implementation of orthogonal code convolution is presented by employing Xilinx and Modelsim softwares. It is found that the orthogonal code implementation improved the error detection upto 99.9%. With this method, the transmitter does not have to send the parity bit since the parity bit is known to be always zero. Therefore, if there is a transmission error, the receiver will be able to detect it by generating a parity bit at the receiving end.

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