Fpga Implementation Of High Speed Vedic Multipliers

Fpga Implementation Of High Speed Vedic Multipliers
Authors : S.Karthik , Priyanka Udayabhanu
Publication Date: 28-12-2012


Author(s):  S.Karthik , Priyanka Udayabhanu

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Vol.1 - Issue 10 (December - 2012)

e-ISSN:   2278-0181


High speed and efficient multipliers are required in day to day complex computational circuits like digital signal processing, cryptography algorithms and high speed processors. Among various methods of multiplication, recently Vedic multipliers are being more efficient. This paper presents a design of high speed 4X4 bit Vedic multiplier architectures based on two different Vedic sutras namely, Urdhva-Triyag and Nikhilam. These sutras meant for faster mental calculation. Among these two sutras Urdhva-Triyag is more efficient than Nikhilam and other multipliers with respect to speed. The most significant aspect of Urdhva-Triyag sutra is that, the developed multiplier generates all partial products in one step. High speed adders are used in the architecture instead of conventional Ripple carry adders thereby reducing the delay further. In Nikhilam multiplier architecture Urdhva-Triyag sutra is used for more efficiency. The Vedic multiplier architectures are coded in Verilog HDL and synthesized using Xilinx ISE 13.3. The proposed multiplier architectures are targeted to Spartan 3E FPGA. Finally the results are compared with conventional multipliers to show the efficiency in terms of speed.


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