Author(s): Santhi Priya Sarekokku , K.Rajasekhar
Published in: International Journal of Engineering Research & Technology
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Volume/Issue: Vol.1 - Issue 9 (November - 2012)
With the rapid development of technology in deep Submicron, the scale of integrated circuit(IC)grows increasingly. Intellectual property (IP) reuse has been taken popularly. This design method is widely applied in the system on chip (SoC) field. The on chip bus design is most cared in IP-reused based SoC design. Several bus standards were proposed. Among those standards, the advanced microcontroller bus architecture (AMBA) is the most favored. ARM introduced the Advanced Microcontroller Bus Architecture (AMBA) 4.0 specifications in March 2010, which includes Advanced eXtensiable Interface (AXI) 4.0.This is very high speed bus. AMBA bus protocol has become the de facto standard SoC bus. That means more and more existing IPs must be able to communicate with AMBA 4.0 bus. Based on AMBA 4.0 bus, we designed an Intellectual Property (IP) core of Advanced Peripheral Bus (APB) bridge, which translates the AXI4.0 transactions into APB 4.0 transactions. The bridge provides an interface between the high-performance AXI bus and low-power APB domain.
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