IJERT-EMS
IJERT-EMS

Design and Analysis of CMOS Two Stage OP-AMP in 180nm and 45nm Technology


Design and Analysis of CMOS Two Stage OP-AMP in 180nm and 45nm Technology
Authors : R Bharath Reddy, Shilpa K Gowda
Publication Date: 26-05-2015

Authors

Author(s):  R Bharath Reddy, Shilpa K Gowda

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Volume. 4 - Issue. 05 , May - 2015

e-ISSN:   2278-0181

 DOI:  http://dx.doi.org/10.17577/IJERTV4IS051024

Abstract

This paper presents the buffered CMOS two stage op-amp which uses 180nm and 45nm process for design and analysis of CMOS two stage op-amp. Keeping 1.8V power supply, 20μA bias current, aspect ratio W/L, slew rate 20V/μs, input common mode ratio constant. The trade-off among various parameters such as Open loop gain, Phase margin, Gain Bandwidth Product and Power consumption are measured. It has been demonstrated that due to recent development through scaling the size of transistors decreases power dissipated through the device also decreases. This design has been carried out in Cadence design tools.

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