Author(s): R Bharath Reddy, Shilpa K Gowda
Published in: International Journal of Engineering Research & Technology
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Volume/Issue: Volume. 4 - Issue. 05 , May - 2015
This paper presents the buffered CMOS two stage op-amp which uses 180nm and 45nm process for design and analysis of CMOS two stage op-amp. Keeping 1.8V power supply, 20μA bias current, aspect ratio W/L, slew rate 20V/μs, input common mode ratio constant. The trade-off among various parameters such as Open loop gain, Phase margin, Gain Bandwidth Product and Power consumption are measured. It has been demonstrated that due to recent development through scaling the size of transistors decreases power dissipated through the device also decreases. This design has been carried out in Cadence design tools.
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