IJERT-EMS
IJERT-EMS

Design & Fpga Implementation Of Reconfigurable Fir Filter Architecture For Dsp Applications


Design & Fpga Implementation Of Reconfigurable Fir Filter Architecture For Dsp Applications
Authors : MAHESH BABU KETHA, CH.VENKATESWARLU, KANTIPUDI RAGHURAM
Publication Date: 25-09-2012

Authors

Author(s):  MAHESH BABU KETHA, CH.VENKATESWARLU, KANTIPUDI RAGHURAM

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Vol.1 - Issue 7 (September - 2012)

e-ISSN:   2278-0181

Abstract

Multi standard wireless communication systems require the reconfigurable FIR filters with low complexity architectures. The complexity of FIR filters is dominated by the coefficient multipliers. A new hardware efficient reconfigurable FIR filter architecture is proposed in this paper based on the proposed binary signed sub coefficient method. Using the proposed coefficient representation method, the hardware requirements for multiplexer units are reduced dramatically with respect to typical methods. ALTERA QUARTUS II synthesis results of the designed filter architecture show 39% area reduction in the resources usage and 15% power reduction over previously reported two state of the art reconfigurable architectures.

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