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IJERT-EMS

An Efficient Implementation Of Floating Point Multiplier


An Efficient Implementation Of Floating Point Multiplier
Authors : ASIYA THAPASWIN PATTAN, V.RAMESH
Publication Date: 25-09-2012

Authors

Author(s):  ASIYA THAPASWIN PATTAN, V.RAMESH

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Vol.1 - Issue 7 (September - 2012)

e-ISSN:   2278-0181

Abstract

Abstract?Thispaper describes an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a multiply and Accumulate (MAC) unit. With latency of three clock cycles the design achieves 301 MFLOPs.The multiplier was verified against Xilinx floating point multiplier core.

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